Multiple clock domains in a FPGA (using DLL's)

I am targeting a Spartan IIE (400E) device with four global clock buffers (BUFG) and four DLL's.

But I need five clock domains 25MHz(clkin, DLL1), 50MHz (clk2x, DLL1) and 30MHz (clkdv, DLL2), 60MHz (clkin, DLL2), 120MHz (clk2x, DLL2) in my design.

I know that it is not allowed to use more than 2 BUFG per DLL.

I would like to use the DLL's to have a zero propagation delay and low clock skew between output clock signals distributed throughout the device. The primary global nets are driven by global buffers (25, 50,

The 30 MHz clock domain (internal) is not so critical, so maybe I can use a secondary global nets?

How can I drive the secondary global nets with an output of the DLL e.g. the 30 MHz?

Thanks in advance.

Generate a /2 enable signal off the 60MHz clock and use this with the 60MHz clock to drive logic at 30MHz.

You could give this a multi-cycle path constraint for P+R, but

Nial

------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design