The Xilinx web page describing the RocketIO serdes mentions in passing that it can support Serial ATA. But I don't see any support for out-of-band signaling, and the serdes voltage swing and common-mode levels don't seem compatible either. So, it seems that significant external circuitry would be required, and it would be kludgy. Is there an appnote for doing this? Dedicated SATA Phy chips seem pretty hard to find. Of course, a real SATA-compatible transceiver in the next generation of the FPGA would be preferable... -Paul
This might be a place to go to an ON NBSG16VS part, and do the power rails to get the vcm into spec, unless you want to AC couple. They can be set from 100mV to 800 mV (you want about 500 if I remember correctly), but don't get the BGA - they are dropping BGA's like crazy (too much lead inductance, you'll make rise time spec, but not by much unless you're very careful) - the QFN's can go to 35ps.
I just looked at the data sheet on Onsemi's web site. How does this part help with OOB? It's just a Differential Receiver/Driver: there's no enable or CM detection. It would only help with levels, which isn't as much of an issue. I don't think you understood the question, or maybe you meant a different Onsemi part.
Anyway, Paul, please beat up your Xilinx rep! I'm annoyed about this too. They prominently say that the RocketIO can be used for SATA applications, but it doesn't support OOB, which is absolutely required. Maybe if enough people bug them they will do something about it!
The on semi part just gets you into the voltage swing - the oob and cmdet functions are going to have to be handled externally also - I used to work for a company that did these things (Wavecrest) and notice that now mindspeed is dumping their parts (last time buys). The serial ATA functions are not going to be well supported by Xilinx - I think that they are trying to get these things tested right now, and being a digital company, I think that they have some marketing people who assume that they can handle this stuff. Obviously, any mention of SATA with these chips has not been well thought out (1.0 ATA spec requires OOB). Mindspeed is dumping this stuff, and I think I'd be looking LSI ways for a while for anything custom. The jitter spec along is going to force these things away from compliance - me thinks you get about a third of a UI at 1.2G for TJ - and the DCM in the part already gives about 100ps - great for CMOS, but until you get a good CDR module, and proper I/O buffers, we're playing with external components anyway.
I'd see if Peter Alfke (he is Xilinx, but I've found him to be knowledgable and honest) knows of any hints, but I think that serial ATA is still best done SiGe with externals. Mindspeed is having some sort of real fun - the telecom market is not giving them the business that they need to keep some parts alive (they are the cores that Xilinx is using), and should be a good source - they make GREAT stuff, but they are dumping this stuff
Side note for Peter - how can you BERT two of these if your clock is only at 100ps RJ? Tektronix and wavecrest are both capable of doing this, but their clocks are under 1ps jitter. You need a thermally stabilized source to do this in my goofy opinion.