I am facing a problem with Dual-Port RAM (specifically RAM: 2 Port) Megafunction in Quartus 4.0 version, which seems to be a common one.
Given the width of the word and number of words is immaterial, my parameters are as follows:
-RAM registers output port q.
-It is set to 'Auto'.
-The other input and output ports and their settings are as follows: Input Ports:
- Data: arrives at frequency 'a' or time period 'x'.
- rden: starts at rising edge and has frequency 'a' or time period 'x'.
- wren: starts at falling edge and has frequency 'a' or time period 'x'. It is invert of rden.
- wraddress and rdaddress: are associated with the same counter (since my application requires reading old data and writing new data simultaneously in one data clock cycle) and change at the same frequency 'a' as of data cycle. Infact, I am serially reading/writing the memory contents, so the counter increments by one at any time.
- rdclock and wrclock: both start at falling edge and have frequancy '2a' or time period 'x/2'.
In such cases, the delay in reading at output comes out to be '3x/4'. But I want this delay to be wither 0 or n*x/4 where n is even integer.
How is this possible?
Thanx in advance.