Hi, Guy's,
I'm not sure if this is the best place to ask but, I am currently learnin VHDL and am trying to design a RAM model with the following spec:
Inputs: A (3 bit address), D (4 bit data), Clock, plus control input(s) a required
Output: Q (5 bit data)
The design contains two units, a RAM (3 bit address, 4 bit data, separat data input and output) and an arithmetic unit (two 4-bit data inputs, on
5-bit output). These should be separate instances in the design.The design should carry out the following functions:
- Write an input D to address A.
- Read from address A (output to 4 LSBs of Q).
- Add contents of address A to input D (output to Q).
I have to use the std_logic and std_logic_vector types throughout.
Any help is much appreciated,
Thanks,
Stephen.