Can I use the Done signal in FPGA to reset my design

Iam using Sparatn II 200 connected to XC18V02 I have founded that the programing of the FPGA takes a long time so that I lost my master reset ... The question is : Can I use the done signal internally to reset my design ?

Reply to
H.Azmi
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Are you using master serial mode? Why does it take a long time ? You can read the number of clock cycles required in the data book. You can start a new configuration by pulling PROG Low. Peter Alfke ===========

Reply to
Peter Alfke

Hi,

I'm guessing he's got a "master reset" signal run out to an I/O pin, and his FPGA isn't in user mode (done with configuration) until some time long after "master reset" has been deasserted.

I would suggest that he simply make sure his "master reset" is used in the FPGA design as an asynchronous reset. This way, all of the flip flops will be initialized to the desired state at the end of configuration (by GSR) and it doesn't matter if "master reset" is asserted or not, for this one time event when configuration ends. On subsequent "master resets" while the user design is active, the reset will initialize the design as desired.

Eric

Peter Alfke wrote:

Reply to
Eric Crabill

Followup to: By author: snipped-for-privacy@hotmail.com (H.Azmi) In newsgroup: comp.arch.fpga

The easiest way to do this is to have a decrementer initialized in the bitstream to all ones; decrement until it's all zero. Now you have an internal reset signal that will be guaranteed asserted for a specific number of cycles after intialization. You can also OR (or AND, if inverted) with an external reset if you don't always reinitialize on reset.

-hpa

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Reply to
H. Peter Anvin

I think the best is to use GSR but I don't know how to use it in my design can you give me example ? knowing that Iam using spartan II 200

Reply to
H.Azmi

Just using the done signal as the reset for the rest of the board could be dangerous. Here is why: The done signal indicates that programming of the SpartanII is complete and correct. If the configuration of the FPGA was not correct (i.e. the CRC that is performed failed) the done bit will not be set.

If you are using a PROM and the configuration fails than your whole board will be in reset. So what do you do now? Depending on your situation this may or may not be catastrophic. If you also have a controller/processor on the board which is stopped from operating from this case you cannot recover. That may or may not be OK, again depending on your situation.

Board power up and control needs to be thought about and designed up front--this is especially true with SRAM based FPGAs that do nothing on initial powerup and take time to load.

Opinions expressed are my own and may or may not reflect any other human or organisation. Use at your own peril.

~

Iam using Sparatn II 200 connected to XC18V02 I have founded that the programing of the FPGA takes a long time so that I lost my master reset ... The question is : Can I use the done signal internally to reset my design ?

Reply to
James Morrison

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