Hello,
assembling an EDK 3.2.2 design I encountered some difficulties:
- The peripheral reset signals of the Processor System Reset Module are not assigned properly. I declared a peripheral reset port of width 3 in the MPD file: C_NUM_PERP_RST = 3 and assigned the modules reset signals to the port in the MHS file PORT Peripheral_Reset = module1_reset & module2_reset & module3_reset
The auto-generated system.vhd file contains the lines: peripheral_reset_vec(0 TO 0)