Quartus II - Disabling the Optimizer to use gate delay

Hi Vadim,

Building delay chains is not recommended. You can use LCELL buffer as shown below to force a route through two lcells.

module test (in,out); input in; output out; wire lcaout; lcell lca (in,lcaout); lcell lcb (lcaout,out); endmodule

Hope this helps.

Subroto Datta Altera Corp.

Hello Vadim,

In VHDL, enter the following:

signal delay_gate : std_logic; attribute keep : boolean; attribute keep of lval_rowdel_delaln : signal is true;

Similar construct exists for Verilog.

This turns delay_gate into an LCELL of whatever is feeding it. Quartus doesn't remove LCELLs, unless Remove Redundant Logic Cells is set in your design, which by default it is off - check your .qsf or under Assignments/Settings/Analysis&Synth/More Settings.

If you want to keep a redundant register, set REMOVE_DUPLICATE_REGISTERS to OFF for that register.

HTH,

-- Pete

Oops cut and paste error ... my other msg should read:

attribute keep of delay_gate : signal is true;

-- Pete