signal delay_gate : std_logic; attribute keep : boolean; attribute keep of lval_rowdel_delaln : signal is true;
Similar construct exists for Verilog.
This turns delay_gate into an LCELL of whatever is feeding it. Quartus doesn't remove LCELLs, unless Remove Redundant Logic Cells is set in your design, which by default it is off - check your .qsf or under Assignments/Settings/Analysis&Synth/More Settings.
If you want to keep a redundant register, set REMOVE_DUPLICATE_REGISTERS to OFF for that register.
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