binary constant divider theory

Hi SD u can do the timing analysis for ur design using Xilinx's Timing Analyzer. This tool gives a detailed description about the critical path covered on ur design.

Sourabh,

it seems that you are actually performing a multiplication by 2 ( x / 0.5 = x * 2) and so the sign remains the same band the other bits are one position left shifted. to me it seems that your module should not give proper result if a(6) = 1 and even the value of o(0) should be always zero but this happens only if a(6) = 0... so now i am a bit confused...

does it give any clue?

andrea

For simple multiplications and divisions:

X > m = X / (2^m)

Be sure not to lose the sign bit on multiplications (i.e. overflow).

Looks like you're trying to do X >>2 i.e. a multiplication by 2 (but the o(0)

Paul,

My second question was a general question about combination delay, not specific to the design we are looking at. Yes, I think theres a fix I need to make in this code. I would apprecu=iate if you could aadvise on the combination delay question/

Thanks

y

understanding

Paul,

I guess I'm really bad at expressing myself. Ok so heres one last try of explaining my question. Lets say I do have a design which involves lot of logic (multipliers, adders, subtractors etc etc). My question is whats the best way to find out the exact delay using free Xilinx WebPack? the synthesis report does give me a max combination path delay, is that what I should be looking at?

Thanks in advance.

"SD" schrieb im Newsbeitrag news: snipped-for-privacy@c13g2000cwb.googlegroups.com...

Sythesis reoprt is just a rough estimate, often ways wrong. What you need is the timing report after Place & Route. If you set some timing constrainst in your UCF, the timing analyzer will check those and write out a report if the deign meets your requirement or not. A simple timing constaint is

NET my_clock period = 10ns;

This tells the timing analyzer checks if the logic between your FlipFlops need less than 10 ns propagation delay (including clock2out and setup times). There are much more timing constraints, but this is getting more complex.

Regards Falk

Falk,

Thanks for the input. What if my design is a pure combination logic (unregistered), I mean no clocks. So now whatever the synthesis report gives me, is it still way off the mark??

"SD" schrieb im Newsbeitrag news: snipped-for-privacy@l41g2000cwc.googlegroups.com...

More or less. The problem is, that the timing analyzys after synthesis has no clue about placement and routing. Yes, it can estimate an average placement/routing delay, but this is still not really a valueable number. If you want to know the propagation delay of your logic, use timing constaints like

TIMESPEC "TS_my_delay" = FROM PADS TO PADS 20ns;

This will tell te timing analyzer that you need a combinatorical delay of

20ns or less from all input pads to all output pads. You can also have a look into the asynchrounous delay report, it listas all net delays. But can be tricky in a big design.

Regards Falk