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adding real UART to xilinx ultracontroller design.

Hi all, I have been using the xilinx ultraContrller design pretty succesfully but I need to add/change the peripheral setup. The design comes with 32 bit GPIO and a software based serial communication and some memory, none of which are connected on the PLB or OPB. In fact there is no OPB or PLB instantiated in the design.

The serial communication drivers are blocking and I would like to change this to nonblocking. I believe i need to add a plb UART to make it nonblocking. Is this correct? and to do this I also need to add a PLB bus.

Does it make more sense to create a new EDK project and add a plb bus, plb uart and plb gpio instead of builing on what I have already. I have tried this but have had very little luck getting the connections correct and then figuring out how to do the memory layout.

Suggestions for a newbie to using EDK successfully would be much appreciated.

Thanks

Matt

Reply to
Matthew E Rosenthal
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Matt, I tried this before with no success. The Amount of changes needed to add a PLB or OPB causes a lot of errors unless you are pretty experienced with EDK. Also, I posted this same question to the embedded processor forum on the Xilinx website, here is the post and response: Joe "UltraController and UART" 3/10/04

10:26am
Reply to
Joe

Matt, I tried this before with no success. The Amount of changes needed to add a PLB or OPB causes a lot of errors unless you are pretty experienced with EDK. Also, I posted this same question to the embedded processor forum on the Xilinx website, here is the post and response: Joe "UltraController and UART" 3/10/04 10:26am Good luck, Joe

Reply to
Joe

Matt, I tried this before with no success. The Amount of changes needed to add a PLB or OPB causes a lot of errors unless you are pretty experienced with EDK. Also, I posted this same question to the embedded processor forum on the Xilinx website, here is the post and response: Matthew Ouellette "UltraController and UART" 3/10/04 10:26am Good luck, Joe

Reply to
Joe

Matt, I tried this before with no success. The Amount of changes needed to add a PLB or OPB to the Ultracontroller causes a lot of errors unless you are pretty experienced with EDK. Also, I posted this same question to the embedded processor forum on the Xilinx website, here is the post and response: Matthew Ouellette "UltraController and UART" 3/10/04 10:26am Your best bet is probably to create a new project and add the required busses. Try to find a MHS that has the PPC and UART from someone (I'm in a different lab now or I'd send one to you.) Then you will need to create a custom IP core for your logic using the IPIF. Good luck, Joe

Reply to
Joe
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Another possibility is to add the UART as a DCR peripheral rather than a PLB/OPB peripheral. This will keep the UltraController small, but still allow you to expand the capabilities beyond a 32-bit input/output through the BRAM Port B.

Then it is up to you how you decide to implement the UART. (Add a FIFO, etc.) You will need to access it using assembly instructions (over the DCR) but you can now have a non-blocking read/write access to the UART.

Cheers,

Mark Xil> Matt,

Reply to
Mark Sasten

In Xilinx Application Note 759 we created a DCR to OPB bridge and then instanitated a OPB Uartlite. This also kept the size of the UltraController small while giving us the same functionality that you are looking for.

Check out the PPC sub-system in XAPP759 as an example on how to implement the Uartlite in hardware.

Shalin-

Mark Sasten wrote:

Reply to
Shalin Sheth

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