verilog to blif(lut)

Hi All,

Can anyone suggest a method to convert verilog file into blif (LUT) format. Does altera or xilinx support this file conversion ?. Kindly help me in this regard

Thanking you in advance

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Standard synthesis and place-and-route tools?


Reply to
Andy Peters

What is blif format? You are probably talking about synthesis tool, aren't you?


Reply to
Vladislav Muravin

"Vladislav Muravin" schrieb im Newsbeitrag news:bccEe.10218$

BLIF - Berkeley Logic Interchange File

some Lattice tools produce and use BLIF as example there is blif to vhdl tool within lattice toolchain


Reply to
Antti Lukats

Although I've never tried this myself, I suspect the easiest route will be to produce an EDIF file (an industry standard design format) from whichever synthesis tool you prefer to use, and then convert that to BLIF.

A quick google lead me to this tool:

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Hi All,

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Wow, a blast from my past! I wrote that as a project quite a while ago. It was intended to take an EDIF file plus a library and convert it into a BLIF file. It was only tested on EDIF produced from MaxPlus II, and could handle only pure logic designs (no RAMs, not sure about adders, etc.).

The problem with EDIF is not parsing it (that's easy). It's knowing what the underlying library is.

The sort of flow you could use is: (1) Synthesize to some target architecture (2) Dump an EDIF netlist (3) Write a library file for edif2blif (and no, I don't really remember how any more) (4) Run edif2blif and hope for the best.

Good luck!

Paul Leventis Altera Corp.

Reply to
Paul Leventis (at home)

Hi Junaid,

Quartus can output blif, and can read & synthesize verilog. So it can act as a verilog to blif converter. Quartus can either output "raw gates" blif before any optimization has occured, or it can output a blif netlist of the circuit technology-mapped to k-input-LUTs after all optimization of the logic has occured.

The upcoming release (for use with Quartus II 5.0) of the Quartus University Interface Program materials includes detailed documentation on exactly how to output blif from Quartus, as well as many other things: sample benchmark circuits, XML descriptions of Altera's FPGAs that can be used to write place and route tools targeting them, even a way to output Verilog from SIS so you can bring circuits from SIS back into Quartus for further analysis or verification.


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for details. Version 5.0 hasn't been posted yet, but it should be very soon. Transfering data from Quartus to SIS (and vice versa), including blif output from Quartus, is described in the documents/quip_synthesis_interface.pdf file in QUIP 5.0.

Until QUIP 5.0 is on the web, here is a quick overview of how to generate blif from Verilog:

To generate un-optimized (raw gates) blif, add the following to your file:

set_global_assignment -name INI_VARS "no_add_opts=on; opt_dont_use_mac=on; dump_blif_before_optimize=on"

Then run


The blif output will be in .blif

If you want a blif output of the circuit after the logic has been optimized and technology mapped to LUTs and FFs, use this settings line instead of the one above:

set_global_assignment -name INI_VARS "no_add_opts=on; opt_dont_use_mac=on; dump_blif_after_lut_map=on"

There are some limitations on what circuits can be output to a blif netlist, since blif is not as general as Verilog. See QUIP 5.0 for details.


Vaughn Altera [v b e t z (at)]

Reply to
Vaughn Betz

Dear Sir,

Thanks a lot. I followed the information given by you and converted verilog to blif file. But while I am converting the same to the net file one error is coming. Allow Unrelated Blocks to be Clustered: Yes Connection Driven Clustering: No Timing Driven Clustering On Timing Analysis Done Every 32000 blocks Allow Early Exit: No Tradeoff Parameter Alpha: 0.75 Delay Through Blocks: 0.10 Intra Cluster Net Delay: 0.10 Inter Cluster Net Delay: 1.00

Error: Net #35 (null) has no driver and will cause memory corruption. I have sent one mail in your mail address kindly see the mail and help me to solve the problem

Reply to

I emailed Junaid the answer to this a while back, but should have posted to the group in case others hit this. Better late than never ...

Quartus 5.0 writes out blif files where unused LUT inputs are connected to gnd. Some tools (e.g. Vpack below) do not like this, since they don't know what gnd is. To get rid of the gnd LUT inputs, read the blif file into sis and write it back out. Now each LUT will be of minimal size (i.e. if only two inputs were used and two were grounded, sis will write out a 2-input LUT only).

For more info on writing blif files out of Quartus 5.0, see the QUIP

5.0 documents at
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The blif writer is documented in the documents/quartus_synthesis_interface.pdf file.


Vaughn Altera [v b e t z (at)]

junaid wrote:

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