What I'd do is this:
First of all, you have a fast S&H (or series of them, ala Tek 7S series sampling heads -- which is worth reading up on anyway), and you send a pulse to the S&H exactly when you want it to do its thing. Then the ADC chomps away on it at its leisure.
Now, for low speed stuff, you don't need anything, you can run the ADC wide open and trigger in software. But as bandwidth goes up, more hardware will become more important.
To generate precise timing, you need a fast comparator to set trigger level (which comes from a DAC), an edge detector (rising/falling slope trigger) and a variable delay. And probably some gating, for stuff like delay and holdoff.
The important features are synchronizing the chip with the trigger, or vice versa, and adjusting timing on the fly. So that's what the variable delay does. For long times, you can use software, or something onboard the uC, easily enough; for finer control, you will need hardware. What you might do is use both, using hardware as a vernier control over the coarser uC timer. That'll let you generate really wide ranges of timing without using much hardware.
For the programmable delay, what you might do is use a single fixed capacitor, a small (constant) charge current, a fairly steep discharge current, and a comparator against a variable threshold (from a DAC). If more range is necessary (over 1:100, let's say), you can program the charge current, or use FET switches to select different timing capacitors.
Remember that, to use the hardware part as, for instance, the 8 LSBs of the timing number, you want the DAC's output to read, say, 2.5 to 5.0V, for a capacitor charging linearly from 0 to 5.0V. That way, when the low byte overflows, it goes back by half, while the software one goes up by the same time interval. Actual amounts, of course, depend on how you've timed the capacitor, what voltages it covers, etc. etc....
Tim
Deep Friar: a very philosophical monk.
Website: http://webpages.charter.net/dawill/tmoranwms
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news:e0c5c3d1-2e62-4381-8868-db859d7977d9@h11g2000yqb.googlegroups.com...
> I\'m looking at how to design a digitizing oscilloscope. Sticking an
> attenuation/gain stage to a fast ADC and an FPGA is easy enough (more
> or less). But I\'m curious about how digitizing scopes measure the
> interval between the trigger and the first sample. I\'ve heard this
> refered to as a trigger time interpolator and several other names.
> The
> question is, how does it work and how do I build a reasonably
> accurate
> one with technology available to a moderately skilled hobbyist?
>
> The descriptions I\'ve seen talk about a circuit that charges over the
> interval from the trigger to the first sample clock, then the charge
> is measured (usually through something like an integrating ADC). I
> read this at first glance as an SR latch (S is the trigger, R is the
> sampling clock), charging a capacitor, measuring the capacitor from
> an
> ADC. But my instinct tells me I won\'t get any useable level of
> accuracy from this simple combination.
>
> Anyone know anything about how these are built?
>
> Thanks,
>
> Chris