PLL synthesizer chips

On a sunny day (Thu, 19 Oct 2017 10:39:16 -0400) it happened Phil Hobbs wrote in :

I have been playing a bit with the ADF4350: From the datasheet: The ADF4350 allows implementation of fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers if used with an external loop filter and external reference frequency. The ADF4350 has an integrated voltage controlled oscillator (VCO) with a fundamental output frequency ranging from 2200 MHz to 4400 MHz. In addition, divide-by-1/2/4/8 or 16 circuits allow the user to generate RF output frequencies as low as 137.5 MHz. For applications that require isolation, the RF output stage can be muted.

That said, you can alse use a Raspberry, it has a(3?) build in synthesizers[s] with a wide range:

Yes I remember that MC14152, was in many projects at that time.

If one needs a higher frequency than a uP can handle one could probably use some external VCO controllable over SPI or I2C and use an undersampled version of the output into the ADC as the error signal for the feedback loop; I'm sure someone has written a white paper on something like that

"VCO" in quotes

I'm only interested in _good_ synthesizers. ;)

Cheers

Phil Hobbs

I recently designed a board that has two LMX2571's. We got the eval board and played with that; performance was phenomenal, under 1 ps RMS jitter (basically our measurement floor), frequency settable to parts-per-trillion. It has as I recall three internal VCOs, GHz range stuff.

What's nasty is the math it takes to program its zillion SPI registers... some serious numerical lifting. The eval board comes with a PC app that obviously does all that, but TI won't reveal their code, or even the algorithms, so one has to read the massive data sheet and prowl Wikipedia for best-rational-fraction algorithms and such. Well, we have code now.

I expect to have the actual on-board synths running in a day or so. We are gradually bringing up the board, with FPGA and Linux code. Heavy lift.

Been using an ADF4351 as a synth in my lab. BTW, my great uncle lived in Sleepy Hollow, back in the 60's. Used to scare the crap out of me as a kid, headless horseman and all. He lived right next to the bridge the horseman couldn't cross.

I'm now designing an AC power source/amplifier, for testing synchros and resolvers and LVDTs. The internal sinewave source is a tiny ARM cpu doing software DDS out of its on-chip DAC. Here's my PCB placement so far:

Of course, my frequency range is a bit limited. Aircraft "wild power" is maybe 250 to 800 Hz.

Maybe not good enough for lazer beams, but using code to compensate for inherently lackluster/underpowered hardware has a long tradition called The Automotive Industry

Have you considered DDS? I like the AD9833, nice digital phase control and such. Though in the end I had to abandon it and do a discrete design because the $5 they charge for the IC was too much.

I talk about DDS, but the bit I'm working on is PLL-related.

Thanks

Phil Hobbs

LTC6948

the frac N dividers and segmented on chip VCOs are wonderful these days. m

DDS is fine for some things, but it doesn't (often) hit exact frequencies and tends to have a lot of jitter and really weird frequency-domain spurs. The required lowpass or bandpass filter is more hassle than the chip itself.

The SRS clock generator, a fairly decent box, starts with DDS then cleans it up with a narrowband (crystal, I think) bandpass filter, then does some integer PLL stuff.

Am 19.10.2017 um 16:39 schrieb Phil Hobbs:

AD9901 phase detector. No surprises; its Kp does not collapse exactly at the lock point. (unlike some charge pumps that work best with an artificial phase offset)

cheers, Gerhard

Spurs, yes, but I never had much jitter issues with DDS. Provided that the crystal oscillator was clean. The lowpass is just a simple row of caps and inductors, easy as long as you don't need to go to the frequency limit. If the inductors must all be on the same side they should be rotated by 90 degrees from one to the next.

The last device I used from SRS was a 0-100kHz analyzer. Let's not go there ... long story short my lowly Samsung NC-10 netbook with its built-in sound chip clearly showed a noise problem that the SRS couldn't even see.

SRS is our archrival in digital delay generators. After we introduced our box, they redesigned theirs to almost meet our specs [1]. Their redesign still has 7-segment red LED displays, which they use to spell out words. Blast from the past! It's fun to try to figure out what they are trying to say.

I always wanted to write a book in 7-segment. Like the guy who wrote a novel without using the letter 'e'.

John Larkin wrote on 10/19/2017 2:21 PM:

Only the poor DDS designs have excessive jitter or excessive close in spurs (which I assume you mean when you use the technical term "weird"). Retain an adequately large phase word and you will have as much spur headroom as you wish.

Seems like the PLL could do the filtering in the filter at the input to the VCO. Then the DDS could be used at any frequency. If the DDS is fixed frequency, why not just use an XO?

It may be helpful to specify what it is going to be used for. A lot of those "clock generator" PLL or DDS designs are fine for the purpose of generating some clock frequency for a digital system, but when it is going to be used as a signal in a radio receiver or transmitter the requirements are a bit more stringent...

On a sunny day (20 Oct 2017 08:14:39 GMT) it happened Rob wrote in :

About that, I have used the raspi frequency generator to do SSB reception on an AM receiver by placing the carrier in the right position. No problem understanding what was said. It depends a bit, some frequencies have indeed a wobble that can be prohibitive.

The SRS box, the CG635, specifically claims low phase noise and jitter. The narrowband crystal filter cleans up the DDS uglies but preserves the fine frequency resolution. DDS has awkward spurs, but you can pick a small frequency range that doesn't have close-in artifacts.

Like a lot of complex designs, it could be replaced nowadays with a $10 synth chip.