Andre, You posted an article saying you want to simulate your design but you have components that can not be easily reproduced by models. Give SeaHDL/SimHDL a try at
formatting link
It was originally intended for people doing radio DSP. The design is done is a "C-like" code with VERILOG extensions. It then outputs a VERILOG file and a schematic. The schematic is imported to a simulator which can simulate RF signals, noise, multipath, etc. It lets you see the design in a hierarchical format, browze and plot out any nodes in the design.