Hi, I am designing an AMBA-AHB Master interface.As per the spec ,there is a delayed version of the HMASTER bus is used to control the write data mux.So my doubt is ,whether I should have one clk delayed hwdata from haddr or both can be driven at the same time..It's pretty urgent to make up the decision...
AMBA works in a pipelined manner ... data from a master (HWDATA) should always be valid one cycle after the address is valid. Data should then be held until HREADY is sampled ... when the slave has signalled that it is complete.
The delayed version of HMASTER is only used in the arbiter for the AMBA bus.
By definition, AHB has a separate address phase and data phase that is to be presented on the bus on two different clocks. Masters are responsible for driving those two different phases. In the case where there are Muxes controlling what is presented to the rest of the bus, you can get away with having a master drive both address and wdata on the same clock. In this case, the Muxing scheme that is used must insure that the two phases happen when they are supposed to. One way to do this is to generate a delayed version of HMASTER from the arbiter. The original HMASTER should be the selector for the address and control signals and the delayed version should control the mux for wdata.
Hi Subroto, Thanx for the info.Actually if you are designing only the master interface for AHB to plug-in to the existing AMBA bus then you are not very sure that how the internal arbiter is designed(for delayed HMASTER signal),so can i presume that there will be delayed select signal for wdata mux and drive both haddr and hwdata on the same clock or myself should have that addr-data delay??