capacitor placement

locking capacitor placement with Ultrascale plus devices. I am new to the c ompany and I am up against "we always do it that way".

causes horrendous other routing issues. Assuming the link is a sine wave th en the "edge" takes 83ps (half the period) to launch which is about 11mm so the cap is already electrically not at the "historically done" TX pin. I w ould therefore like to put the caps at the connector end. I have tried sugg esting that PCIE cards seem to put the caps at the edge connector.

to help my argument.

It is worth thinking about why it could matter where the capacitor is placed. There will almost certainly be some impedance mismatch at the transmitter end of the transmission line. The receiver end is more likely to be accurately terminated. In such a situation, there will be negligible reflection at the receiver and the signals will be clean. If you add a capacitor this may cause a mismatch due to its large size relative to the signal tracks and there will be some reflection from it. There could be multiple reflections between the source mismatch and the capacitor mismatch leading to variations in the frequency response of the transmission line.

In extreme cases this looks like a comb filter. By keeping the capacitor close to the source mismatch the frequency of the first null or dip is kept as high as possible, hopefully above the system operating range.

If you can't achieve this, then try to make the capacitor match as good as possible by using the smallest possible package size, preferably one where the width of the capacitor is similar to the track width.

John

If they are DC blocks in the signal path, on an impedance-matched trace or pair, it doesn't matter where they are.

blocking capacitor placement with Ultrascale plus devices. I am new to the company and I am up against "we always do it that way".

causes horrendous other routing issues. Assuming the link is a sine wave t hen the "edge" takes 83ps (half the period) to launch which is about 11mm s o the cap is already electrically not at the "historically done" TX pin. I would therefore like to put the caps at the connector end. I have tried sug gesting that PCIE cards seem to put the caps at the edge connector.

t to help my argument.

True, but if one end is better matched than the other then it can make a difference (which may or may not be important).

John

How?

DC blocking capacitor placement with Ultrascale plus devices. I am new to t he company and I am up against "we always do it that way".

hat causes horrendous other routing issues. Assuming the link is a sine wav e then the "edge" takes 83ps (half the period) to launch which is about 11m m so the cap is already electrically not at the "historically done" TX pin. I would therefore like to put the caps at the connector end. I have tried suggesting that PCIE cards seem to put the caps at the edge connector.

ment to help my argument.

If the transmitter circuit is mismatched and the receiver is well matched and the capacitor introduces a mismatch there can be multiple reflections between the transmitter and the capacitor. This will introduce nulls in the frequency response of the transmission line at frequencies depending on the spacing between the driver circuit and the capacitor. The equivalent in optics is the Fabry Perot interferometer.

If the capacitor is well matched to the transmission line then of course its position doesn't matter. With the very small capacitors now available this may well be the case. Also, with FR4 at around 10GHz the losses may damp any resonances enough that they become unimportant.

John

John