I am looking to use FPGA's as specialized coprocessors to increase performance on different applications. I would like the lowest latency possible to memory. I have only found options with PCIE and HyperTransport, but I was hoping to find something similar to this which I assume would have lower latency than PCIE or HyperTransport: (
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). However it seems that product is no longer in production.
Are there any similar products to the above link? I suppose a related question is, how much lower latency would there be for an FPGA on the FSB instead of PCIE or HyperTransport?
There were 2 or 3 companies manufacturing accelerators that were aimed at sitting in a second processor socket. For companies that have used this technique the problems of keeping up with socket changes was always going to be a problem. The other problem is that the second socket on most motherboards, and maybe all, has dissappeared. Main reason for that is multi-core processors that don't need 2+ sockets.
PCIe latency can be a big factor if you doing a HPC system that only does "small" commands, instructions or functions because the PCIe latency costs you much more than you gain. "Big" commands, instructions, or functions are usually ok. Chained systems or systems where the processor is only a manager usually work well. That's why in our HPC systems, using our Merrick and Broaddown family boards, we make features like 1G and 10G Ethernet directly available to these boards that cuts out the PCIe structure.Similarly we now do real world sensor interfacing for these systems through our Lamachan2 board so there is minimal latency.
There are usually other ways to tackle most problems but it depends on what you need to achieve. Here we do a lot of different things depending on a customer system requirements and rarely is the same approach used for any 2 customers.
Intel AGTL+ FSB is dead and buried. Also, I am not sure that even when it was alive the latency was really lower than HyperTransport. AMD HTX slots also close to non-existent. Intel QPI made short appearance in the desktops but was quickly killed by more integrated solutions and, by now, exists only in servers. Besides, QPI is not very narrow source synchronous parallel bus that, in its latest incarnation, runs at 6.4-8.0 GT/s. I.e. even the most modern FPGA will have very hard time talking to it :(
Overall, low latency off-chip co-processors look like technological dead end. Sorry. You better start looking for a way to live with relatively high latency of PCIe interface.
Sometimes you can't live without low latency, but reasonably often you can do it pipelined. That might mean doing two or three of whatever you are doing instead of one, using separate data streams.
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