PCIe over cables

Jan 29, 2011 9 Replies

We're proposing a controller box to a customer. The customer suggested that he include an XMC module on one of his PowerPC embedded computers and talk to our FPGA over PCIe.



This might be in his end:



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At this point, I have no idea what might be on our end. Probably not a connector and wires into our FPGA. Maybe some sort of transceiver/equalizer chips. Maybe another of those boards, above, poked into an XMC site on our board, so we have clean regenerated PCIe into our chip.



Does anybody have experience with PCIe over cables? Seems a little scary.



John



Yep. It works.

For initial bringup on one of our products, we bought a card that plugs into a PCIe slot on a pc. The card has the retimers and equilizers for its four lanes. They sell a cable that connects to their card, and the same connector on the other end. The cable I used was 1 meter long and went to our board that has a V6 FPGA. No problem once I changed the coupling caps on our board from 1000pF to 0.1uF to allow the so-called low frequency "beacon signalling" to get through. Didn't realize this until I rtfm.

I'm not sure what the max cable length could be, but certainly is easier if you go Gen1 (2.5Gbps per lane) rather than Gen2 (5Gbps per lane).

Bob

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Look at USB 3.0 which is electrically almost identical to PCIe Gen2 which means there is nothing scary about PCIe over cables.

Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.com

"John Larkin" wrote in message news: snipped-for-privacy@4ax.com...

PCIe version 2.0 supports cables up to 10 meters in length running at

2.5 Gb/s. It looks like it uses LVDS transmitter/receiver pairs.

I'm surprised I haven't seen more thingy's with PCIe and long cables.

Cheers

Thanks. On your end, did you go directly from the cable connector into your FPGA? No silicon between?

Whose card did you use?

John

We go right in to the GTXs on the FPGA. If you plan on doing this, be very careful on the lane assignment at the FPGA if you're going to use the Xilinx built-in core. It takes some digging and a decoder ring to get it right.

I'm pretty sure it's this card. We got the cable from them, too, but it was manufactured by Molex (iirc).

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Bob

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John Larkin wrote: : Does anybody have experience with PCIe over cables? Seems a little : scary.

Not experience yet, but I'm interested, too. I just purchased the TI ADS1675 reference design board (not powered it up yet) which uses the Opal Kelly XEM3010 FPGA module to connect the converter to a PC via USB2.0 . I notice that Opal Kelly is now delivering the new XEM6110 which is supposedly plug-in compatible at the module end, but uses PCIe-over-cable as the communication method. Therefore I'm thinking this as an escape route, should it turn out that the ADS1675 board cannot sustain the maximum sampling speed over USB (probably it does) - it might be possible to just plug in the PCIe version to the ADS1675 board and write some code.

I need to write my own VHDL code anyway, and Opal Kelly claims that they provide the communication related IP blocks with the card, so that the user VHDL can be interfaced with them. But you never know how it works in practice and how many gotchas there are without actually trying.

Anyway, I'm wondering if there are similar FPGA integration modules available, which bundle the communication IP with the module, but use USB3.0 instead of the PCIe? There may be a larger variety of USB3.0 hosts than PCIe hosts available in the future.

Regards, Mikko

Our customer is using a CPCI PPC SBC, with an XMC slot available, so we'll stick with PCIe over cable. Enough acronyms?

If we discover anything interesting along the way, I'll post it here.

And if anybody might be in a position to give us some serious help, we would be interested. We have to do a monster project in about three months, and if the PCIe-to-FPGA thing could be offloaded, we could probably get the customer to fund it.

John

I've seen other boxes using DVI-style connectors.

Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------

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