spartan3 pci above 33MHz

Hi all

I am interfacing a spartan 3 to a device that happens to use PCI. As the two devices will be about an inch apart with a point to point bus I'm curious about the right buffer to instantiate, particularly as bandwith calculations suggest that I need to run this bus at about

50MHz and the datasheet says that only pci_3v_33 exists in the IOB when pci_3v_66 exists for virtex 2.

Presumably on a standard PCI card the requirements for clock, req and the other few point to point signals also aren't electrically PCI. In particular clock is almost certainly provided by a standard LVCMOS clock driver so what IOB settings to people use?

Thanks in advance for any suggestions.


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Interestingly enough table 20 in this datasheet lists PCI66 for spartan-3:

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Also, PCI is specified for rather high bus loads and wire length. With a single load and 1cm of wiring you should be able to run a pci33 core with pci33_3 I/O at 50MHz.

My PCI core even worked in all our systems when I removed the timing constraints which caused it to miss the specification by 8ns.

Kolja Sulima

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Kolja Sulimma

Thanks for taking the trouble

Note to self ALLWAYS check that I am using the latest datasheet before posting to the world like a right plonker!

In my defence the new datasheet is only 2 weeks old. I only downloaded the datasheet about 3 weeks ago and searching for "PCI" found no reference to 66. It now finds 3, none of which are explicitly in the Revision History!

Hence my question over which IOBs people use on the single load signals. If XILINX provide the right IBIS models I will see if the PCI33 IOB uses less power and hence easier decoupling etc.

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The Spartan-3 family is fully compliant with the 33 MHz PCI specifications for both 32-bit and 64-bit busses. The PCI core for Spartan-3 is available from the Xilinx web site. The associated reference design targets the XC3S1000-4FG456C FPGA although the design can be adapted to other part/package combinations.

Xilinx Real-PCI Web Site

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Although Spartan-3 FPGAs easily perform at 66 MHz clock rates and beyond in most applications, Spartan-3 FPGAs do not meet _all_ the electrical and timing requirements of the 66 MHz PCI specification. The PCI specification defines a specific timing budget for 66 MHz operation over a PCI backplane loaded with other PCI-compliant cards.

In open systems, full compliance with the PCI specification is required to ensure interoperability. However, in embedded designs, it is possible to create custom PCI timing budgets. Custom timing budgets enable system designers to reduce cost by using less expensive FPGA devices like the Spartan-3 family. For Spartan-3, a 66 MHz PCI implementation is possible simply by "borrowing" from one timing parameter to meet another.

For example, PCI is a common chip-to-chip communications protocol. If the two PCI end points are co-located on the same board, the design does not need to account for signal propagation over the backplane and through the PCI connectors. A reasonable board layout can reduce the board propagation delay from the allotted 5 ns to an actual value of 2 ns or less, in order to meet the Spartan-3 FPGA setup time requirement. The system designer would need to verify that their custom timing budget meets all the requirements of his or her embedded application.

I have a separate document that I will send you that includes all the relevant PCI 3.0 timing and which parameters that you can ignore if you're on the same PC board. In summary, you likely can use the Spartan-3 33 MHz PCI design at 50 MHz if you're not traversing bus sockets, etc.

--------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs

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--------------------------------- Spartan-3: Make it Your ASIC

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Steven K. Knapp

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