I am designing a system which is consdering using PCI as backplane bus, which has six slot and 3 inches between each. I Can't decide If I can route a pci clock longer than 2ns(i.e. 12inches). The pci spec says the maxium clock skew between two pci devices is 2ns ,but not says the maxium length of the clock signal. Any ideas. Thanks.
The clock length is usually irrelevant (which is why its not specified). Use a clock generator and splitter to drive each PCI clock independently (the clock is *NOT* multi-drop) and equalize their lengths on the backplane, as well as the plug-in card. Watch the trace length on the cards (it's usually a constant).
I vaguely recall the spec specifying pF loads. Something like 100pF total. Memory serving, they mention that there is 10pF reserved for each board, 10pF for each connector. With a chipset on one side and a bridge on the other (each also with 10pF) that leaves 80pF total. At
20pF per inserted card (board and connector), this is 4 slots. But I seem to recall the classroom teacher telling us also that if you can use low-pF connectors it is possible to push things a little. You'd still have to assume 10pF for each inserted card and 10pF for each end, so that is 80pF for six cards, without the connectors added in. Leaving 20pF/6 or about 3pF per connector. Not sure if that is possible, but if my memory from the classroom remains correct, then that just _may_ be possible to find.
The spec gives examples based on "loads", where an add-in card is two "loads" and an integrated device is one "load", with a maximum of ten "loads". It is just an example though. The designer has to do the analysis.
I think they told me that a "load" was 10pF. I forgot to mention that if there is no bridge load, that's another 10pF added up. So 6 slots may leave 30pF/6 or 5pF per connector, if there is only one chipset side and no bridge (and allowing 10pF for the chipset itself, which may or may not be correct for it.)
My recollection is that the pF loading _was_ the spec to analyze towards. The 100pF total was for 33MHz, memory serving. I think that went down to 50pF for 66MHz. (Do they specify things in terms of current, now, rather than pF loading?)
Nope. It's not in there. There are signal integrity and timing requirements, nothing about "loads", "pFs", or "ins". I should look to see if I still have a spec on a disk somewhere (no one really uses PCI anymore).
I don't know what they did. They likely put a SBC right in the middle, so the end slots were only 15 slots away. Still, the line lengths are huge between nearest and farthest, so yeah... probably bridged, but not at every four slots.
Six is about all I've ever seen done, at least that attempted to meet spec. I'd think it would be hard to go much beyond five, with two bridges on the segment, but perhaps six is possible. Fifteen, never.
At most, with the slower PCI speeds, you get three sockets per branch, then you have to bridge.
One of the Macintosh clones (of that brief period when Apple licensed out their OS) had six PCI slots (I think it was a PowerTower Pro), where the nearest Macintosh (8500?) had only 3. I tracked down a problem with a video board, that was initilized by ROM code only if it was in one of the rightmost three sockets. After booting, it saw the native PCI sockets and the ones on the other side of the bridge, but DURING boot, it only saw three PCI sockets, because that's all the Mac ROMs were written for.
Video had to be initialized before the GUI and other OS parts, so three sockets were completely useless for video cards. All the PCI sockets functioned AFTER boot, but that was too late.
If we concern about the capcitance here , I think the trace and vias on the backplane(which is so long introducing much capcitance ) must be concerned too.
The CompactPCI spec use maxim an eight slots backplane on 33Mhz but works well. And the distance between two adjacen slots is 0.8inch).
what I am confusing is how much infuence of the length of the bacplane on the signal integrity of the backplane. If the lengh is still shorter than the 10 ns signal settling time. i.e. 18inches here for 6 slots(the clock line is longer than 2 ns equivalent length ). will it beyond the settling time?
PCIe is much easier. I recall 11 or 12 inches max for PCI. You have to figure out what the return time is for the bus, including connector capacitances and such. It?s a reflected wave bus, the last card is the first to get switched. Here an old edn article. Tprop (round trip) must be 10ns.