Hi,
I am having PCIX Core in FPGA. Hence after power on reset, it takes some time (FPGA configuration) to get the PCI-X Core logic. Lets say it is 2 seconds for example.
after this time only, logics being realised and it can respond to PCI configuration Cycles.
My question is, after power ON when the PCIX controller starts its enumaration process. ie., reading configuration space
Thanks in advance.
Regards, Muthu
Hello,
Once the power becomes "good" there is a minimum 100 ms delay before the RST# signal deasserts.
Unless you are designing a 32-bit PCI card, you MUST have the FPGA finished with bitstream loading before RST# deasserts. This applies to any compliant PCI-X design regardless of bus width, and also to any PCI design that is 64-bits wide.
The reason for this is that your FPGA design MUST be loaded so that it can detect the busmode initialization pattern, which is broadcast at the deassertion of RST#. If you miss this, you are in big trouble...
Once RST# is deasserted, you then have 2^25 or 2^27 cycles, depending on the bus frequency, until the first configuration access to your device.
Eric
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