PCI compliance ?

For me, posting about Cin/ DCI problems is all it takes to set him off.

Go read that thread I'd linked to as an example of his posting etiquette, which went something like this:

Peter A. : Series DCI has zero additional system power Brian : Except for the 200 mW/bank overhead Austin : ( leap in with guns blazing ) Brian : ( return fire )

Some questions are best left un

One step removed, working with the guy who's on the committee, to build the T&M equipment needed for verification, or the equipment needed to test the equipment needed for verification.

There are certainly politics, but claiming that a basic PCI electrical loading specification is rigged specifically to exclude FPGA vendors is a bit (insert non-offensive adjective of choice here).

Brian

After last checking them in June '05, I summarized the poor state of the DCI Power Answer Records over here:

Brian

Austin,

You've already called me a novice, no need to repeat yourself.

Check the message timestamps, I posted that response to you about ten minutes BEFORE I replied to Ray.

Scattered, incomplete, and inaccurate Answer Records are not proper documentation of such a serious problem as has V2 DCI.

We've had that discussion before, too.

I don't want an apology for past documentation problems, I want you (Xilinx) to fix those problems so others don't bang into the same things on old & new parts.

It didn't really bother me that I hit those problems in early 2003, three years after the V2 product launch.

Or that a months long webcase produced no solid answers.

Or that six months later, all the CR's I'd filed hadn't corrected the documentation/Power Estimator/Xpower problems.

What really ticked me off is that when I personally took the time and effort to summarize all those problems in that "LVDS_25_DCI Top Ten List" post here in Oct. 2003, you launched the first in a series of attacks on me, when I've mentioned related Cin/DCI Power/FreezeDCI problems here on the newsgroup.

Brian

Austin,

IIRC, 2A extra per board, or about 400 mA extra per chip @2.5V VCCO, for both bank overhead and parallel termination error, five 2V250's, about 20 LVDS_25_DCI per chip.

Documentation thereof can be found where?

Funny how my facts of yesteryear have become your facts of today.

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[Austin_2004]: Freeze DCI has nothing to do with it. [Brian_2004]: Using FreezeDCI in the V2 affects both the behavior and repeatability (config-config & part-part) of static DCI power consumption, both for per-bank overhead, and particularly for per-input parallel terminators [Austin_2006]: Freezing it also stopped the reference resistor search, which could (randomly) increase the ref resistor power (in V2).

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[Brian_2004]: As each bank has its' own independent CCLK type oscillator driving the tap adjustments, you end up with a random sampling of the possible DCI adjustment states for each bank.

As I understood it, the newer devices having DCIUpdateMode were going to cleanly stop the DCI updates in all banks at a known state rather than randomly halting them as with FreezeDCI.

[Austin_2006]: Standards which crossed a bank also had issues, as the controllers were independent (one for each bank, not synchronized).

This has since been fixed in later families so that freeze is done better

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[Austin_2004]: DCI updating is only an issue when you cross between two banks, and even then only with the parallel interfaces where it adds some small amount of jitter [Brian_2004]: On the other hand, with FreezeDCI on, the resulting random DC offset for the parallel terminators will probably cause problems for the single ended standards with accurate terminator VTT requirements (whether in one or multiple banks). [Austin_2006]: which led to some problems with specific applications (primarily wide buses with extremely critical timing using HSTL or SSTL parallel standards).

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Brian

References: [Austin_2004]:

[Brian_2004] : [Austin_2006]:

Hi Just use level shifters between the PCI and FPGA .... Have made that m slef and works fine ... Send me an email for schemtics

Regards, p

with

5V