PCBs for modern FPGAs.

All,

After reading and contributing to a few interesting threads recently about PCBs for FPGA designs, I thought I'd post about the technology I've been using for the past 3-4 years. My job involves getting a lot of high density circuitry into a small space, and so awhile back I decided to use microvias (laser drilled vias) to pack more stuff onto my boards. The surprising thing was that the boards worked out cheaper for my application than if I hadn't used this method.

I'll explain why, but you might first want to download the picture at

formatting link

My stackup is ten layers, like this:-

1) signal 2) signal 3) ground 4) signal 5) signal 6) ground 7) signal 8) signal 9) ground

10) signal

There are laser drilled microvias between layers 1 and 2. The only other vias are through vias, i.e. from layer 1 through all layers to layer 10. This means there's still only one mechanical drilling process during manufacture. What you can see in the picture you downloaded is how to route out all but four of the signal pins on banks 2 and 3 of a V2PRO in a FG676 package without using any through vias, just microvias between the two layers, blue and light green. The track and gap distance is 4mils or 100um. With this technology you can go 8 rows deep on a 1mm pitch BGA without using through vias.

In no particular order, here are the advantages.

It's no problem at all to put microvias in a pad. The microvia is just a

2mil deep pit that fills with solder, unlike a through via which must be plugged to stop the solder wicking away.

You can use fewer signal layers because the signal paths out from the FPGA aren't baulked by through vias.

You can use fewer (or no) power layers because it's possible to fit a lot of bypass caps on the back side of the board from the FPGA, with through vias direct from these to the FPGA power balls. (In the picture you can see the ground (green) balls and Vcco (yellow) balls. By the time this board went out, there were two through vias for each power ball.) With a conventional board, the through vias don't leave space on the backside to fit (m)any caps.

You get to have a decent ground plane(s) for your BGA devices, not one turned into Swiss cheese by a myriad through vias. Bye-bye ground bounce.

You gain board area all over the back side of the board simply because there's less space used by the vias from the topside.

Compared to a through via, the SI of a microvia is much better. After all, it's only 1/30th the length of a through via.

The components can be closer together, reducing SI issues.

I always follow some rules when routing FPGAs this way. Like these:-

Draw lines from the four corner balls to the very centre of the part. Don't let any layer 1 or 2 traces cross these lines, it always seems to screw things up.

Be prepared to put much more effort into the PCB. This doesn't work well unless you're prepared to sit down with the layout person and swap pins on the FPGA as you route things up to align with other components on the board. For diff pairs be prepared to swap Ps and Ns. You can fix up the inversion inside the FPGA.

The upshot is, for a lot of my applications this saves me 4-6 layers over a conventional board. (For others, it simply makes the job possible!) This more than compensates for the cost of using the laser vias. Also, I don't want to hear about warpage! Although the stack looks asymetrical wrt ground planes, the stack up *is* symmetrical wrt cores and prepreg layers. I've had no problems whatsoever with warpage on 1.6 mm boards of up to 8x6 inches.

I'm by no means saying this is the best solution for every board, but it worked really well for me. It's certainly worth asking the PCB fab house about the cost, yield etc.

Best, Syms.

p.s. I'm glad I'll have microvias when I come to route up this bugger.:-

formatting link
page 239 of 262 , FX60, FF672 package! The pads are all over the place.

Reply to
Symon
Loading thread data ...

When you say it was cheaper, you ended up with a 10 layer board with micro-vias, what was the alternative? I have a 10 layer board that I want to reduce to save money. How many layers can be saved by using micro-vias with BGAs?

--
Rick "rickman" Collins

rick.collins@XYarius.com
 Click to see the full signature
Reply to
rickman

Rick, I typically save about 4 to 6 layers by using microvias. My boards go into hand-held portable equipment so board space is at a premium, which is why the boards are so dense. To answer your question, in my experience, you would certainly be able to convert a ten layer conventional board to eight layer microvia board.

1) signal 2) signal 3) ground 4) signal 5) signal 6) ground 7) signal 8) signal

Microvias between layers 1 and 2. Power routed with localised split planes.

To suggest anything further, it depends on what size FPGAs/BGAs you're using. Are you willing and able to swap a lot of pins around on the FPGA to route to the other devices on your board? How many of the 10 layers you currently use are power/ground planes? Cheers, Syms.

Reply to
Symon

Symon,

What are the speeds of your clocks and signals both within your FPGA and external? Are you getting and passing EMI compliance testing? Have you tried or considered using thin layers between power (also signal in your case) and ground planes instead of or in addition to bypass caps? Do you do SI/EMI simulations or just build these boards? :)

Thanks for sharing this! Awesome stuff!

Thanks, Ken

Reply to
Kenneth Land

What's the diameter/restring of micro vias ? I don't see them in the 'capabilities' of the pcb supplier I'd like to use. They however have blind vias with hole diameter down to 50µm. I guess that would work.

What is warpage btw ?

Sylvain

Reply to
Sylvain Munaut

Where do you get your prototype boards fabbed?

Reply to
Tim

The current board uses one ground, one power, split with some extra power traces running on a signal layer. I had been planning to keep that the same. Sounds like you are suggesting two ground layers and another for power, no?

Do you have a ball park number for the additional cost of microvias? I guess I would need to plug that into some quote web pages to see.

--
Rick "rickman" Collins

rick.collins@XYarius.com
 Click to see the full signature
Reply to
rickman

Symon,

Awesome. Great posting.

We have recently begun using buried vias (fully internal vias blind to both sides). I do not know if these are laser drilled, or not. The cost was not a factor. It is imperative to use this technology for the

10Gbs transceivers (for better matching), as just one example of their need. As well, it has all of the other benefits you detail (regarding having better overall SI due to less "swiss cheese").

Austin

Reply to
Austin Lesea

I use 600+MHz clocks and > 600+Mbit data to and from the FPGA. I always use the 'divide-by-two' DCM thing and DDR IOBs for this. There's also 2.5 GHz/Gbps in some places on some boards, not to the FPGA of course. I've not tried the Rocket I/Os yet, although they are wired up on a couple of boards.

Yes. Most of the problems come from inter board connections. I'm trying to move to using the Rocket I/Os for this. The microvias are a big help for getting termination resistors right where you want them. I use packs of 2 (1mm square) and 4 (2mm x 1mm) resistors for this, with vias in the pads.

in

No. I reasoned that the tiny amount of (admittedly v. high Q) capactitance you gained by doing this is pissed away by the inductance of the vias, tracking, balls, and tracking on the FBGA substrates.

HyperLynx is my friend! Or it would be if I could get IBIS models of the LVDS_DT inputs! When I mentioned earlier that I've had EMI problems with interboard connections, I had a processor address and data bus from another board that connected to a V2PRO. By the time the 3.3V signals got to my FPGA, I had overshoot to 5.5V and undershoot to -2V before the diodes clamped the signals. The uP board designer had used sub-ns buffer-drivers from IDT to drive the 50MHz bus over a 2mm pitch connector. (Those IDT buffers, they're really quick!) So, demonstrating to the guy who spends the R&D cash, I lifted the power pins to the IDT parts and put 50 Ohm resitors in series. The overshoot vanished, leaving the undershoot unchanged. When I put resistors in series with the ground pins of the IDT buffers, the undershoot went as well. When I used HyperLynx to model the system, I got the same results. Purchase Request for HyperLynx was signed!

Reply to
Symon

Hole is 6mils, land is 14. 150um and 350um in new money. ;-)

use.

It's a made up word that means how much the board warps or bends after, or even during, reflow and the like. Too much prevents the devices soldering properly, which is why the datasheets always have a coplanarity spec. for the pins. I guess BGAs are probably less affected by this than QFPs

Reply to
Symon

Hi Tim, These guys helped me develop this stuff. Highly recommended, intelligent and open to trying out new stuff! And they also used to beat us every year in the annual inter-company cricket match!

formatting link

I've since moved jobs/continents, so I now use

formatting link
HTH, Syms.

Reply to
Symon

Yes, once I saw all these different core and I/O supplies appearing, I decided to concentrate on the ground layers and track/local-plane the powers. It also makes analysing the SI stuff a lot easier, because there's always a nearby ground plane for every signal's return current to travel along. Check out

formatting link
for an example. Sounds like your board is already very busy wrt signal layers. Must be pretty dense.

Yeah, the cost depends on so many things. You've gotta work with your PCB house to work out what's best. I guess what I'm trying to say is that by spending on the laser vias, you save on the layers. Another point is that cheap overseas PCB fabs often can't produce these boards. They're geared up for mass produced boards. But your local PCB company can. So sometimes, for the right application, you end up with a cheaper board, produced locally with all those support, turn-around time, quality benefits that brings while keeping the bean-counters happy too... Cheers, Syms.

Reply to
Symon

Hello Symon,

I'd like more informations about the stackup you use, what are the thickness of the layers/prepreg ? What are the consequences of not having the top layer referenced to a 'near' plane ?

Thanks,

Sylvain

PS: Note I wrote both to the news group and bcc to you to make sure you see this answer, as the topic is not recent.

Sym> All,

Reply to
Sylvain Munaut

thickness of the layers/prepreg ?

'near' plane ?

see this answer,

about

density

microvias

thing

hadn't

route

FG676

100um.

using

FPGA

lot of

vias

the

went

conventional

bounce.

all,

Don't

on

board.

inversion

Reply to
Joanne Moores

Hi

Thanks, I'd appreciate it.

I'm not working right now with dense bga ( just a small FT256 and PBGA272), nor a lot of layers ( 6 or 8 ).

And I'm trying to find what would be the best for my application (cost and perf, ...) between either using 4 mil traces or microvias. Both allow to avoid lot's of vias in the "critical" zone under the bga where I need place to put bypass and big vias for power. It also reduces greatly the impact on SI.

It's also interesting for me for future applications where I might have to use denser parts.

Using 4 mil traces, I can escape most of the FPGA pins without via at all and connect them quickly to where they belong (one DDR chip using point to point connection for the critical nets). The downside is that they have a higher impedance (more like 105 ohm using 35µm copper). That's a little over the "recommended" for PCI (60-100 ohm) but still since my PCI bus is on an internal layer I could try to change the trace width before and after the vias (here I just want the vias out of the way). Wait a minute ... or I could use a thinner layer ...

Using microvia, I can also escape de BGA without loosing my clean power planes and there I can escape and spread all the signals with 6 mil traces.

I'll have to simulate some tests and discuss that with the board house as well.

Anyway, great technique,

Best regards,

Sylvain

Reply to
Sylvain Munaut

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.