This is a symptom that I think was introduced in edk 6.2 sp2 and apparently is also present in edk 6.3
The problem is that as the main system clock (generated by a DPLL and constrained) is being passed through modules such as lmb_cntlr which is taking the system clock and puts out a BRAM clock (purely pass through). The BRAM clock will be unconstrained and break our system timing. The timing report under "Requested" shows "N/A".
I can manually edit the system.v and change the input clock to the BRAM to be my system clock - that will fix that particular clk net, but push the problem to some other net. Before EDK 6.2 sp2, I was able to meet timing with only 5 minutes of compile time. Now I can't meet timing anymore after running for more than 30 minutes.
Is there a fix for this ?
Thanks ! rudi ============================================================= Rudolf Usselmann, ASICS World Services,