Hi !
According to Xilinx documentations, the PLB bus is limited to
100MHz. We have a need to run at higher frequencies, 125MHz and even 250 MHz. We are Using a VP20 -6 FPGA.If I do not use the EDK flow and any of the EDK modules, but just a PPC405 and write my own modules for internal and external memory management, etc, is it possible to run the PLB at higher speeds ?
I know the PPC405 has a OCM bus, and that supposedly supports up to 375 MHz system clock. However the overall bandwidth is listed as 500 MBytes/sec. So I presume there are some sort of other limitations there.
My main concern is overall data throughput. The speed of the PPC405 is irrelevant as it is used for maintenance tasks only ... we could even use microblaze for that. It's just that we need for the CPU to be able to access the memory data bus as well.
Any suggestions, recommendations, war stories ?
Best Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services,