Hi,
I use V2P70 to control DDR SDRAM (HY5DU561622CT-J) in the clock of 166MHZ. The row address of this chip if [12:0].
The strange thing is that sometimes one of ddr chip will regardless parital row address[12:9]. Then this chip size is become from 16Mb * 16 to 1Mb * 16.
What kind of wrong operation will make ddr chip become this error. since the error will recover after power off-on.
BTW, reconfiguation FPGA or reinit DDR SDRAM can not help DDR chip leave from this error.
sincerely, seyor
HI, I think I have found the problem. The board supports dynamic config FPGA via PCI I/F. Since software set FPGA's user reset to active before re-config FPGA, the DDR chip will not become error again.
reset it, before re-config it. is this a rule for XILINX? :)
regards, seyior
HI,
I think I have found the problem. The board supports dynamic config FPGA via PCI I/F. Since software set FPGA's user reset to active before re-config FPGA, the DDR chip will not become error again.
reset it, before re-config it. is this a rule for XILINX?
regards, seyior
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