Package constants (VHDL)

May 30, 2011 2 Replies
F

Historically I have used a VHDL file to embody the constants in a design where possible using meaningful names which can be easily changed.



library IEEE; use IEEE.STD_LOGIC_1164.all; package constants is constant rck_freq : integer := 30; end constants;



I require two sets of constants according to debug or otherwise, I might try:



package constants is if debug = 1 then constant rck_freq : integer := 10; else constant rck_freq : integer := 30; end if; end constants;



But ISE coughs. Can someone enlighten me on the correct way of doing this, if possible?


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K

Create a function that implements the selection... function sel(Cond: Boolean; If_True, If_False: integer) return integer;

Then use the function to set the constant... constant rck_freq : integer :=3D sel(Cond =3D>debug =3D 1, If_True =3D> 10, If_False =3D>30);

You'll likely find the 'sel' function to be very useful for simple

2=3D>1 muxing operations that you will also find it useful to override the function with various other forms... function sel(Cond: Boolean; If_True, If_False: std_logic) return std_logic; function sel(Cond: Boolean; If_True, If_False: std_logic_vector) return std_logic_vector; function sel(Cond: Boolean; If_True, If_False: std_ulogic_vector) return std_ulogic_vector; etc...

Kevin Jennings

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F

0,

Many thanks indeed for such a quick reply. It's now sorted.

There are times when I don't find VHDL very instinctive and confess I'm not very au fait with functions. Many thanks again.

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