OPB <-> WhishBone wrapper (opb_wb_wrapper at opencores)

If we have a way to plug wishbone signal between the wrapper and the ipcore(wishbone one) imported from the wizard i can live with this. Even is it's not automaticaly connected together.

If we can add thoses connection in a easy way i can live with this !

How can i connect them manualy ?

regards

Jonathan

Hi all again,

if i see this in the system.vhd:

-- Internal signals . . . . . signal gpio_top_0_wb_dat_i : std_logic_vector(31 downto 0); . . .

gpio_top_0 : gpio_top_0_wrapper port map ( wb_clk_i => net_gnd0, wb_rst_i => net_gnd0, wb_cyc_i => net_gnd0, wb_adr_i => net_gnd8(0 to 7), wb_dat_i => gpio_top_0_wb_dat_i, wb_sel_i => net_gnd4(0 to 3), wb_we_i => net_gnd0, wb_stb_i => net_gnd0, wb_dat_o => open, wb_ack_o => open, wb_err_o => open, wb_inta_o => open, aux_i => net_gnd31, ext_pad_i => net_gnd31, clk_pad_i => net_gnd0, ext_pad_o => open, ext_padoe_o => open );

opb2wb_0 : opb2wb_0_wrapper port map ( OPB_Clk => sys_clk_s, rst => mb_opb_OPB_Rst, opb_abus => mb_opb_OPB_ABus, opb_be => mb_opb_OPB_BE, opb_dbus => mb_opb_OPB_DBus, opb_rnw => mb_opb_OPB_RNW, opb_select => mb_opb_OPB_select, opb_seqaddr => mb_opb_OPB_seqAddr, sl_dbus => mb_opb_Sl_DBus(192 to 223), sl_errack => mb_opb_Sl_errAck(6), sl_retry => mb_opb_Sl_retry(6), sl_toutsup => mb_opb_Sl_toutSup(6), sl_xferack => mb_opb_Sl_xferAck(6), wb_data_o => gpio_top_0_wb_dat_i, wb_data_i => net_gnd32(0 to 31), wb_addr_o => open, wb_cyc_o => open, wb_stb_o => open, wb_sel_o => open, wb_we_o => open, wb_ack_i => net_gnd0, wb_err_i => net_gnd0, wb_rty_i => net_gnd0 );

is opb2wb_0->wb_data_o and gpio_top_0->wb_dat_i connected together ?

if yes i thing i have found a way to connect easily both signal :)

regards

Jonathan

"Jonathan Dumaresq" a écrit dans le message de news: Sh6Rd.30695$ snipped-for-privacy@charlie.risq.qc.ca...

Use the "Port" tab in the "add/edit cores" dialog windows like what you use to connect clock & reset signals together ...

Connect all signals like "wb_stb_i" to the "wb_stb_o" of the other core, pretty easy ...

Sylvain

"Sylvain Munaut" a écrit dans le message de news: 42150d44$0$28532$ snipped-for-privacy@news.skynet.be...

Yea that is what i have done. I have plugged all the net together and for the gpio wb_clk_i plug to the sys_clk_s and wb_rst to sys_rst_s.

I have remove the led part of the edk project and want to replace it with the wb_gpio. So i have connected all the wire to the real pin on the fpga in the ucf file.

Now i woule like to know how can i write to the wb_gpio register.

This is what i think that should be modify:

change the wb_gpio address to 0x2000000 ? or change the wrapper to the address of the wb_gpio ?

I probably miss something again or this is suppose to work like i describe ?

regards

Jonathan

any news Sylvain ?

have you play with wb_gpio ipcore ?

regards

Jonathan "Sylvain Munaut" a écrit dans le message de news: 420fb7ae$0$22479$ snipped-for-privacy@news.skynet.be...