Hello,
I'm fairly new to this - just got started running the testbench for the Opencores Ethernet core. I'm using Modelsim SE64 Plus 6.0b in a Solaris
5.10 environment.
I get a few test failures when running the testbench:
Heading: MIIM MODULE TEST
At time: 8991769 Test: TEST 10: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )
*FAILED* because Data was not correctly written into OR read from PHY register - control register
***************************************************** Heading: MAC HALF DUPLEX FLOW TEST
At time: 483196167 Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) *FAILED* because Transmit should NOT start more than 1 CLK after CarrierSense and causing Collision
At time: 484976407 Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) *FAILED* because Transmit should NOT start more than 1 CLK after CarrierSense and causing Collision
At time: 955522987 Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) *FAILED* because Transmit should NOT start more than 1 CLK after CarrierSense and causing Collision
The above tests also failed a number of times for other reasons, so I was wondering if I was missing anything. I checked the opencores forums, and it seemed like someone had similar problems, but there were no answers to that thread. I also ran it on an earlier version of Modelsim and got the same failures. I don't know if I perhaps didn't configure something correctly?
Thanks.
Pei