is this a good idea

Its the worst idea I have seen on this newsgroup to assume the state of registers at power up in an ASIC. BAD BAD BAD, 300 lashes with a broken O'scope lead for the assumption. Watch your simulator. It should have unknown in registers that were not initialized. Some registers initial state is a don't care, some are very critical, it all depends on your design.

Jer

This is a very bad idea. Bad/no design for exiting reset state will cause your ASIC/FPGA to be unreliable - sometimes it will start working, sometimes not.

In addition, most simulators HATE it - they will start with everything in "unknown" state. Reset-recovery problems are very hard to simulate (same category as meta-stability problems - not really deterministic), so that the design appears to be OK in simulation.

Best practice:

• EVERY flip-flop should be explicitly reset (including FFs in I/O pads).

• Resets are global nets, treated exactly like clocks. Most FPGAs allow using dedicated clock nets for reset - recommended.

• Each clock-domain should have its own reset. The trailing edge of the reset signal should be synchronous to the clock and shouldn't violate reset-recovery timing for any FF. (use a synchronizer for reset - the probability of two FFs stuck in meta-stable state is much lower than one or two of a set including tens of thousands FFs in the clock-domain).

• Just to make your design clear, use the same signal-name everywhere for every reset net (also good practice for clock nets).

Can't I just tell the foundry that I need the regs to be zeroes at powered on? Anyone done this before?

No, reset is a functionality which needs to be designed in. There are several reasons for this. One is that some methodologies require that there be no asynchronous resets and and initialization be synchronously loaded. But this requires a clock to work. Also async reset flops are usually larger and slower than non-reset flops so it's a plus if you don't need them. Also it doesn't depend on the foundry but the cell library you use.

The best solution is to use asynchronous resets with external reset being synchronized with two flops per each clock domain where the reset signal is needed. This way you can time the reset recovery constraint and there are NO metastability issues to be dealt with and two flops are all that's needed. The two flops used in reset synchronization are similar but not the same two flops which are used in cross clock domain transfers.

Hope this helps,

Muzaffer Kal

ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations

all

on?

The foundary would have to use a special register primitive that is supported by a power-on-reset mechanism added to your circuitry. The ASIC house would need a different netlist. Do you want them doing some of your design?

Also - MAJOR caveat: the Xilinx devices do NOT always power up registers to zero. If the register is implemented with an FDS or FDSE primitive (synchronous sets) the register powers up to a logic one.

As far as dedicated reset nets, Xilinx has warned many times in the past not to rely on the dedicated net because the skew across the device - in older devices, at least - could be large compared to the clock cycle. The suggestion in another post to synchronize your reset to each clock domain is superb; releasing reset is usually an asynchronous event that can send only some of your circuit out of reset on the first clock cycle.

I plan to use the BUFGMUX primitives to bring my FPGA with well-defined power-on states into operation by enabling the clock to all elements at the same time rather than rely on an asynchronous power-on reset OR explicit snchonized resets to each and every friggin register, using significant routing resources and some logic resources (by eliminating the synchronous set/reset from my synthesizer's bag of tricks). I would never parlay this FPGA specific method to an ASIC.

--

--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com

"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

No, at least for VHDL it should not. For STD_LOGIC types it should have "uninitialized"=U if no initial value was given. This is different from "unknown"=X. As all xilinx flip-flops have an initial value, the VHDL code should explicitly initialize the registers to '0'. (Or '1', if you use a register with preset or initialize it to 1 in the UCF file)

For an asic design the registers should be initialized explicitly to 'X'.

That way your simulation should match the behavour of the FPGA/ASIC.

BTW: As a CAD developer I do not really understand, why I have to set the power up value in the UCF file when the VHDL line

signal register : std_logic := '1';

tells the synthesis tool all that it needs to know.

Kolja Sulimma