Re: ZCD with no Dflops

There is such a thing as event driven logic, it does not need to be synchronous with a common clock. Synchronous logic is event driven, the defining event being the occurrence of a common clock (edge usually).

I'm certainly no logician, but surfing on "async logic" brings up some interesting discussion that async can result in 40% power savings, but takes more gates to do so. Considering the continual reduction in ASIC feature size, considerable effort is in play for using async in portable devices and in medical implants. The biggest impediment right now to that development is the lack of async synthesis tools. ...Jim Thompson

That's been the problem for decades. Synchronous logic synthesis and analysis separates the issue of logic correctness (pure state machine stuff) from the issue of timing analysis, namely how fast can you clock it reliably. Pipelining is a major tool to fix the problem of the combinational logic limiting clock rates, but pipelined logic is still just logic.

Async logic tangles the logic functionality with the speed issues. I'd imagine that the simulation burden explodes when you do async logic: what had been logical simulation becomes essentially analog simulation. Imagine simulating an analog circuit that has a billion transistors and thousands of inputs and outputs. Now do that over Vcc and process variations and temperature.

Not so. Logic simulation remains logic simulation. Take the student version of PSpice for a test drive and see how the logic simulator works... it'll spit out all the hazards in a nice list.

I would imagine, at least for analysis, that VHDL and Verilog will continue to work. Synthesis is the difficulty.

Billions, and billions, and billions... ;-) ...Jim Thompson

VHDL is not an analysis language, it's a logic description language. Actual gates and flops are synthesized downstream, with other tools, and may look very different from the VHDL when it's actually mapped into specific hardware.

There are VHDL simulation programs, but they usually work from the VHDL itself, not the synthesized logic. What we usually do is sim at VHDL level and do static timing analysis (which is ignorant of the logic intent) after logic synthesis, and hope that the logic synthesis stuff worked.

One could write an async logic design in VHDL - just don't clock anything - but I don't know where you'd go from that, or how you'd verify the final logic. Sounds like a nightmare, which is why nobody has got it to work very well.

=A0 =A0 =A0...Jim Thompson

for that specific implementation

VHDL and Verilog is description language you can describe pretty much anything you like What you'll be analyzing/simulating will at best be a behavioral model with some delay thrown in.

when you start Synthesis all bets will be off, logic might be optimized away implemented as lookup tables etc. etc.

Even if you basically write a netlist of instantiated primitives you can't always be sure what you get

Xilinxs latest show off mega FPGA is 6.8billion transistors ...

-Lasse

I was at a show a couple years ago and I saw a PCB that had 16 high-end Xilinx chips, which were about $6K each at the time. The product was a hardware-based logic simulator, with a typical config having a bunch of these boards inside.

And that was to simulate *synchronous* logic!

"John Larkin" schreef in bericht news: snipped-for-privacy@4ax.com...

Down at the transistor level it's all analog. The combinatorials like the gates can be considered analog and simulated that way but there's hardly a thing to gain. Once you're using feedback building fliplops and other sequential elements, analog simulation become more difficult though not impossible. At this level the elements are still asynchronous but can be used to build synchronous circuits. You can bet, the logic diagrams of the internals of synchrounous counters and the like (hopefully) describe the function, not the internal design. (Which is not uncommon in analog circuits as well.) I'm not certain to what limit you can use analog simulation for digital circuits these days, but it's clear that even a simple small micro cannot be simulated this way. I heard rumours last year about design software to build asynchronous sequential circuits, faster then the synchronous counterparts, but I couldn't find it and the rumour died.

petrus bitbyter

Nope. Jim has no opinion, since I am not a logic designer and never claimed to be.

I do approve of Fields jerking you around, though it's getting tiresome. You are indeed suffering from brachycephalic rectumitis (otherwise known as "with big head up butt" :-), and seem hell-bent to dominate this group, preventing all real circuit discussion... claiming nothing can work but what you scribble (and fail to prove).

So I'm contemplating pulling a Woodgate and giving only advice on the LTspice group where it'll be appreciated.

=============================================================== || || || I'll also be available, when time allows, to help people || || who wish to contact me privately... use the "Envelope" || || symbol on my website. || || || ===============================================================

See! You even go out of your way to prove that you are fully infected with brachycephalic rectumitis (otherwise known as "with big head up butt" :-) ...Jim Thompson

You and JF constantly mention things anal and penile. Enjoy!

I _do_ enjoy you being caught with your head up your own butt, but you no longer exist. Bye. ...Jim Thompson