Is it me or quartus ?

Hi Fred,

Thank you for providing the code. The results in Quartus II 4.1, 4.2, are incorrect. If you the "exit" statement in Stop_Sense with a return '0', this will synthesize correctly in 4.1 and 4.2. This problem will be fixed in Quartus II 5.0.The modified VHDL is shown below: library ieee; use ieee.std_logic_1164.all;

entity yy is

generic ( width : natural := 4);

port ( stopcell : out std_ulogic_vector(width - 1 downto 0); isboundarycell, stopnextcells : in std_ulogic_vector(width -1 downto 0));

end yy;

architecture bhv of yy is function Stop_Sense ( IsSigCell, StopNextCells : std_ulogic_vector(Width-1 downto 0); CurrentCell : natural range 0 to Width-1; LookAheadDepth : natural range 1 to 16 ) return std_ulogic is begin L1:for i in 1 to LookAheadDepth - 1 loop if (CurrentCell - i) >= 0 then if StopNextCells(CurrentCell - i) = '1' then return '1'; elsif IsSigCell(CurrentCell - i) = '1' then return '0'; -- replaced exit statement !!!! end if; end if; end loop; return '0'; end;

--signal StopNextCells : std_ulogic_vector (Width-1 downto 0);

--signal StopCell : std_ulogic_vector (Width-1 downto 0);

--signal IsBoundaryCell : std_ulogic_vector (Width-1 downto 0);

begin

StopCells: for i in 0 to Width-1 generate

StopCell(i)