Any guess what this might cost?
- posted
4 years ago
Any guess what this might cost?
Digikey shows the smaller VU13p for $88,766.64.
sweet baby jesus that a big mama jamma!
Next time they give me a nuclear attack submarine or interplanetary spacecraft-size budget I'm going to put a couple of those in the thing.
$135k is my guess
Based on the cell count:
VU13P FPGA Virtex UltraScale 3,780,000 Cells $88,766.64
VU19P 9M system logic cells
9e6/3780000 = 2.382.38 * $88,766.64 = $211,264
From the VU19P blurb:
"While this FPGA is tuned for ASIC/SoC emulation and prototyping, test and measurement, it is also suited for applications such as compute, networking, and aerospace & defense."
To paraphrase British admiral John Arbuthnot Fisher in a letter to Churchill:
OMG
Yes, it is a BFFPGA!
John ;-#)#
"If you're seriously looking at buying this thing you know what it can do and what you're gonna do with it why are we even writing this"
plus
and
Some years ago I worked for a telecom test equipment maker. They produced a piece of gear they expected to sell 10 of. They used a Xilinx chip that cost something like $10,000 (I believe the largest at the time), but sold t he box for $100,000 or maybe it was $150,000. They only needed 10 or 20% o f the FPGA at that time, but didn't want to limit future expansion.
What I want to know is how many of the VU19P on a wafer actually work? At some point the number of defects per feature have to be massively tiny for a chip to work. I think semiconductor processing is one of the miracles of the 20th century and it doesn't seem to be slowing down any in the first 2
0 years of the 21st.-- Rick C. - Get 1,000 miles of free Supercharging
ultrascale-plus
It's four chiplets on an interposer. Xilinx have been using this approach to improve yield and reduce NRE for some years. These are new chiplets though, and (AFAIK) the largest chiplets used by Xilinx.
Regards, Allan
I expect there are significant limitations in signals between the chiplets. Do they treat the design as four separate chips or does the software lump the design together and just treat the interposer as a really slow interconnect?
-- Rick C. + Get 1,000 miles of free Supercharging
If it's anything like the other multi-dice parts from Xilinx that I've used, the designer can treat it as one big fabric, without needing to worry about the interposer (much) at all.
One can also instantiate FF in the interposer (known as Laguna registers) if pushing the Fmax limits. (These have to be instantiated; the tool won't infer them.) I haven't needed to do that (yet).
Allan
It might be one of those "If you need to ask..." situations.
-- RoRo
That's the one-off price. I am sure they come down a bit if you buy a full reel :)
-- John Devereux
I think they come in trays :P
You guys are paying way too much for these. I found 1 in stock for ONLY $77000 !
Lol, they were going to use it in the next gen Fitbit, but they don't want to use the required fine geometry on the PCB because of costs.
-- Rick C. -- Get 1,000 miles of free Supercharging
Nine MILLION logic cells? That's how you emulate a Cray-1... ...in clusters of twenty
They'd have to leave out the many tuned transmission-line delay elements, though.
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.