I write a module as below. Let's look the last ALWAYS block. In the case statement, It worked not as expected when I replaced the binary form's condition(2'b00,2'b01,2'b11, etc) with Parameter(IDLE_PHASE,NONSEQ_PHASE, SEQ_PHASE) each other, the FSM's state(ahb_state) always loop in the last state(default 2'b11). while writing as below, It seemed worked well. Simulating in the modsim SE PLUS 5.6, the waves showed the value of ahb_state always be 2'b00. whys? Thanks
`timescale 1 ns / 100 ps module dma_controller( buffer_address, num_words, enable_dma, dma_req, dma_dir,
//ahb master interface signals reset_n, dma_clk, dma_grant, dma_ready, dma_rdata, rddata, dma_lock, dma_addr, dma_busreq, dma_size, dma_trans, dma_burst, dma_wdata, dma_write, dma_resp, dma_readyo,
//data and control signals for output of DMA set_irq, err_int, wrdata, wraddr, wren, rdaddr, rden, ahb_state );
input [31:0] buffer_address; input [31:0] num_words; input enable_dma; input dma_req; input dma_dir;
input reset_n; input dma_clk; input dma_grant; input dma_ready; input [31:0] dma_rdata; input [1:0] dma_resp; input [31:0] rddata; output dma_lock; reg dma_lock; output [31:0] dma_addr; reg [31:0] dma_addr; output dma_busreq; reg dma_busreq; output [1:0] dma_size; output [1:0] dma_trans; reg [1:0] dma_trans; output [2:0] dma_burst; output [31:0] dma_wdata; output dma_write; output dma_readyo; reg dma_readyo;
output set_irq; output err_int; reg set_irq; reg err_int; output [31:0] wrdata; output [9:0] wraddr; output wren; output [9:0] rdaddr; output rden; output [1:0] ahb_state; reg [1:0] ahb_state; assign dma_write = ~dma_dir; //dma_dir:0->write to sdram, 1->read
reg [9:0] wraddr_sig; reg inc_count;
parameter IDLE_PHASE = 2'b00, NONSEQ_PHASE = 2'b01, SEQ_PHASE = 2'b10;
assign dma_size = 2'b10; //we always do unspecified length bursts to get maximum bandwidth out of the //PLD-to_stripe bridge assign dma_burst = 3'b001;
reg [31:0] buffered_hrdata; reg [31:0] count_dma;
reg dma_req_delay; wire start_trans;
assign start_trans = ~dma_req_delay & dma_req;
always @(posedge dma_clk or negedge reset_n) begin if( ~reset_n ) dma_readyo