Hi expert fellows :) , I would like to get some advices on making a cheap usb analyzer with an cheap FPGA board :
-i only target loww speed / full speed at the moment
- i woudl proceed like this : * cut an existing USB cable, insert a breakoutinteh middle * connect D+ & D- (and GND) to the FPGA pins (i guess impedance aspects are OK since FPGA pin input Z is ~ infinite...) * build the analyzer design using the opencore's USB PHY Core & USB 1.1 Function Core * the design would intercept all USB trafic and would store it onchip , with the possibility of retrieving it on the PC
The main Questions concerns - electric level : i plan to only use D+ using LVTTL but .... - NRZI tackle : how can i rebuild the USB clock from it ?
Any advice welcome !
Have a nice day.