Hello! I'm trying to interface a Spartan-IIE to one of analog device's new ADSP-21262 DSPs. The problem is that my application requires high-bandwidth communication with the DSP, and the DSP's parallel interface expects an _asynchronous_ ram. That's right, it has edge-triggering ALE, RE, and WE lines that are expected to interface to standard static SRAM.
I have been trying to come up with a solution to talking to the FPGA, to no avail. The ALE signal is asserted for only 10 ns, thus oversampling the pins is going to be really difficult (and that's ignoring all the potential metastability issues!) Has anyone ever made an interface like this work? I know on the spartan-series, internal flip-flops can only be gated by the internal clock nets, which can only be sourced by one of the 4 clock pins.
Any help would be appreciated! Thanks,
Steve