1. Home
  2. Field-Programmable Gate Arrays
  3. PPC on Virtex2P: Jumpstart, recommended reading?

PPC on Virtex2P: Jumpstart, recommended reading?

Anyone who has used the Power PC cores on Xilinx FPGAs has undoubtedly paid some dues... I selfishly ask if anyone has compiled a quick set of recipes, lessons-learned, or other guides for *quickly* getting up to speed on using these.

There is no shortage of documentation available, especially from Xilinx. The problem (in classic Xilinx style) is that I don't have all year to read it. Thus, any pointers to the most-recommended, quickly-effective reading material would be appreciated.

Specific scenario and questions:

1) I will soon have a board (with V2P30) on it. I wasn't originally planning to use the PPC, so no buses were routed for external memory. Hope to use on-chip memory only, now that I have a use for the PPC...

2) My tool set includes Mentor ModelSim, Synplicity (Synplify Pro), and Xilinx ISE. Do I need other $non-free$ tools in order to use the PPC? (i.e., Xilinx EDK, etc...)

3a) I first want to instantiate one PPC, load some instructions in memory via ModelSim, tie the PPC core to the rest of the FPGA fabric, and simulate enough instructions to make sure the flow works.

3b) Next, I'd like to create some real short test programs, compile them with gcc (no RTOS required, but if easy to configure and use, that's a bonus), load the memory image (via ModelSim) and simulate.

4) Load the PPC memory instruction via the bitfile when I power up the real hardware, have the PPC boot and start running my code when I toggle an input, so I can watch some outputs toggle on a scope. (Eventually this board will serve as a stimulus/waveform generator for another board.)

5) Where might I find an appropriately configured copy of gcc and libraries?

That's it in a nutshell. I don't expect this to be a one-weekend project, but I don't have all year either. C code, VHDL code, Synplicity scripts, etc... for getting up to speed fast would be ideal.

Thanks very much for *any* help you can provide.

mj

Reply to
jjohnson
Loading thread data ...

I am about to start a similar excercise, but haven't done much yet. I think you should begin with getting the EDK and perhaps one of the cheaper eval boards, e.g. V2Pro LC by Memec Design. Together with the board you will get access to several complete sample projects including C source code on the Memec web site. I am not sure about the simulation. I believe this sort of simulation will be extremely slow.

/Mikhail

Reply to
MM

I recommend starting with the EDK tutorials and the simple Base System Builder (BSB) to get a simple "Hello World" to the uart working. The BSB will set-up the buses, connect the peripherals to them and even set-up the UCF file. If you want to simulate the design, I recommend avoiding the DDR memory and just use the on-chip BRAM's. Furthermore, make sure you read the section in the EDK guide(s) regarding how to configure ModelSim to work with EDK. That's an important section.

In summary, there are no real shortcuts--you'll need to quality time with tools as there is much to ramp-up to.

Good luck!

nn

Reply to
Nju Njoroge

That is fine. Simple programs can run entirely in internal memory.

I suppose it might theoretically be possible to implement only with ISE. But that would be a painful process. EDK provides two things. It will compile simple code into the necessary bitfiles for storage into the internal block memory. And it comes with lots of "cores" for simple modules to attach to the internal processor bus, and a relatively simple method for interconnecting them. EDK is actually rather inexpensive, and you do want it, IMO.

I in fact started with an Avnet board, which included EDK. I think this is the best way to get started.

For simulating systems (using Modelsim), I took the approach of not using the complex PPC models provided by EDK. I do use the provided models for all the other pieces; the PLB bus, arbiters, bridges, etc.

For the PPC model, I basically wrote my own. That was down by creating a PPC wrapper, of which here is an excerpt: entity ppc405_top is generic ( C_ISOCM_DCR_BASEADDR : std_logic_vector; C_DSOCM_DCR_BASEADDR : std_logic_vector; C_DISABLE_OPERAND_FORWARDING : integer; C_DETERMINISTIC_MULT : integer; C_MMU_ENABLE : integer; C_DCR_RESYNC : integer ); port ( C405CPMCORESLEEPREQ : out std_logic; ... ); end ppc405_top;

architecture STRUCTURE of ppc405_top is

begin

PLB_Clk C_PLB_NUM_MASTERS, C_PLB_AWIDTH => C_PLB_AWIDTH, C_PLB_DWIDTH => C_PLB_DWIDTH ) port map ( M_ABus => M_ABus(0 to C_PLB_AWIDTH-1), M_BE => M_BE, ... );

end architecture STRUCTURE;

Notice that about all this wrapper does is to instantiate the entity bd_test. In board test, I have a couple of procedures for reading and writing the bus. They look like this, along with the beginning of the test bench:

entity bd_test is generic ( C_PLB_NUM_MASTERS : integer := 1; C_PLB_AWIDTH : integer := 32; C_PLB_DWIDTH : integer := 64 ); port ( M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1 ); ... ); end entity bd_test;

architecture tester of bd_test is ... begin

testit: process is procedure sread(addr : in std_logic_vector(0 to C_PLB_AWIDTH-1)) is

-- data : in unsigned(7 downto 0)) is begin wait until rising_edge(PLB_Clk); M_request

Reply to
Duane Clark

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.