Dear all,
I need a clarification regarding the glitches in data lines. I am testing a FPGA prototype board by probing out the data line in the debug pin of the board and i found that there are many glitches occured in the data lines on viewing in logic analyser. The data line is declared as "inout" in our glue logic. I gave the data line to the 33ohm series termination resistor and viewing the resistor output in the logic analyser. still the glitch is coming. I also tried with 22 ohm series termination resistor.Still the glitch is there...
Any ideas or suggestion please to remove the glitches......
Thanks in advance,