I would like to spilt up information on a memory data bus into its components. Some text have suggested aliases as a way of doing it. Is it the best way? Modelsim doesn't seem to show the aliases that I define, or, more likely, I don't know how to get Modelsim to show aliases. How is that done?
Brad Smallridge b r a d @ a i v i s i o n . c o m
415-661-068
Consider declaring each vector part separately.
That's the way it is.
-- Mike Treseler
Thanks Mike,
Hmm. I can do that. What though is happening when I do a clockless scheduled event,
mem_input( 7 downto 0 )
Top port signals represent wires. Synthesis requires a process that uses port and process values to update process variables and port signals at each rising_edge(clk).
Such a process might at some point read a port slice: my_upper_byte_v := my_in_port(7 downto 0); And perhaps drive a wide port: my_out_port
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