The Xilinx timing report for XPLA3 CPLD shows maximum operating frequency of 30 MHz for one of our design. But the CPLD is functioning correctly at 80 MHz. If so what does the Maximum operating frequency specified in the timing report signify?
Or more likely, the paths that Xilinx sees as critical are not...
The tools support multi-cycle timing constraints. Did you give it appropriate constraints, or just let it do it's own thing?
Jason
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