Layout examples

If you have solid planes (prefereably closely spaced) you don't need to worry about 'close' in the sense that you probably think of as close. If you have vias to the planes on *very* short tracks, or even better in the pad, then the planes will act as a very low impedance route for your currents. If you think of the time the energy will take to travel from capacitor to chip, the speed of light on FR4 is around 2/3c or 2e8 m/s. In 1ns, this is around 20cm. Halve this for the energy to get back and forth and even 10cm is "close".

I don't have any pictures to hand, but we've done boards like this with 100MHz memory interfaces and 150MHz core DSP clocks that work fine.

Does that help?

Cheers, Martin

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Great comments, Martin.

A point I'd add to the original poster's concerns about the "swiss cheese" ground and power planes you can get with too many vias, some numerical work has shown that - at least for closely spaced ground/power pairs - the added impedance from the swiss cheese under a BGA package (much worse than a QFP) is sub-nanohenry. Don't worry so much about the holes in the plane, worry about the spacing between the planes (smaller is better, 4 mil perhaps?) and good decoupling cap attachment. Two vias are often used on each end of the decoupling caps in high speed designs to halve the impedance to the ground and power planes. The "*very* short tracks" is a noteworthy comment as well; it's easy to make a stiff decoupling cap a bit soft by adding a little track between the pad and via(s).

caps

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Showing my age here.... when I was routinely designing PCBs around 8-10 years ago, I was often given a very hard time by assembly subcontractors if I put vias inside an SMD pad - they used to complain about solder hogging or some such manufacturing folklore. What are the up-to-date design rules for putting vias in or very close to a pad?

TIA

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"Filled Vias" are a process that your raw-board vendor may support and are necessary for in-the-pad vias. You're still right in that unfilled vias in the pad act as solder theifs. Micro-vias (a form of blind via) are even better at giving exceptionally low impedance without acting as a sloder theif but the cost and tool support art two things I'd worry about. Chances are you'll stick with regular vias and get the spacing particulars (capacitor pad to via minimum spacing) from your board assembly house or someone else intimately familiar with the IPC recommendations.

It wouldn't be a good thing to just stick those vias in the pads or a solder-flow away from the pad to act as a nice drain for the solder. These details get lost on those of us who have it ingrained upon us that the minimum spacing shall never be violated. Thanks for keeping the details alive.

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That was the party line many years ago. The problem is that the solder dives into the via (surface tension) so you don't have as much solder left to make contact with the part.

I think it's reasonably common now. It's another tool in the struggle to reduce the inductance on bypass caps.

Check with your assembly house. Sometimes they fudge the hole size in the stencil for the solder paste, or use a thicker sheet to make the stencil.

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Thanks!

Another trick I used that I forgot to mention is to populate groups of caps in a line with one large "pad" connecting them all. Through that pad go 2-3 vias per capacitor to reduce inductance. However, as the illustrious Lee Ritchey would point out I have no science to back up any claim that this is a "good" way of doing things... it feels right. At some point I intend to do some simulation and maybe even (gasp!) some measurements...

Cheers, Martin

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work

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QFP)

Although watch out for accidentally created slots in the ground plane.

If you're not sharing vias for decouplers to keep impedances down and you've a lot of them you can end up creating slots in the ground plane if you've many of them near each other. This can be easily done if your decouplers are neatly arranged on the same X/Y coordinates per side.

Slots are very bad news for high speed signals.

Just something to be aware of.

Nial

------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design

I'll have to disagree with some of this (not meant as criticism, just a point for discussion).

The number I use (and see in most books) for propagation in FR4 boards is

140 to 180ps/in for outer traces and about 180ps/in for inner. That would mean about 1.4ns/20cm. Operating at 100MHz with, say, 1ns edges, means that a cap 10cm away would not be able to deliver significant current for the first 0.7ns of the edge, which pretty much hoses you. This is under ideal conditions, ignoring capacitor frequency-dependant characteristics; mounting-related inductance; trace/plane inductance; board/pin interface issues, etc.

Because of this and more, I think that 10 to 20cm is far from close (that sounds funny) for high speed design. The characteristics of the caps and the mounting/routing methodology can make this a serious issue. There are interesting threads and authorithative information about this very subject on the signal integrity list.

For my last design truly labored over this and took the approach of writing a custom power distribution system simulation tool in order to get a handle on what was going on. Things get serious once you stare down at the prospect of hundreds of pins switching simultaneusly at a given edge rate. And that's what's important, the edge rates, not the frequency. The thinking can be abstracted to using a bunch of caps (the decoupler array) to charge another set of caps (the output traces) through the board-to-chip-to-board interface.

If you start looking at the behavior of capacitors as a function of frequency (and, in isolation of board layout/mounting effects) you'll see that the C and L induced self-resonant behavior can play interesting tricks with what a cap can really do. Of course ESR and ESL are frequency depandant themselves, although it is nearly impossible to get this data from manufacturers.

Beyond that, I find that the field turns "religious" real fast. There are three basic approaches:

1- Do it the way we've been doing it 'cause it seems to work 2- Use a range of caps to cover the frequency (ehem, edge) range 3- Use only two or three a couple of values to cover the range 4- If it looks good during layout it should work.

#1 is folklore and may only have merit if a knowledgeable engineer setup rules conservative rules that can be followed by those working on new designs independently. I find that many think that the old 0.1uF capacitor rules could be adequate for high-speed design when, in reality they are just about useless. The same applies to a certain range of tantalums. So, for my money, option #1 is not a great solution unless you know where it came from, how it got there and what the constraints might be.

#2 is promoted by one school of thought within the SI community. It is perfectly valid, of course. However, I don't see it as manufacturing/BOM friendly. The idea of stuffing a board with a dozen different decoupling capacitor values is not something I look forward to from many perspectives. The theory here is that, by being intelligent about the choice of caps, their mounting and routing, you create a very low impedance "bucket" to cover the edge rates for the design. Like I said, valid, but not my cup of tea.

#3 is also supported by a sect within the SI community and happens to be what I chose to do. The idea here, loosely speaking, is to form the aforementioned "bucket" with just a few values. The value of the capacitor is not as important as the frequency domain characteristics of the same. This is part of the problem today. Cap manufacturers are begining to be pushed by SI experts to address high-speed decoupling needs and produce (and quantify) caps that are friendlier to this approach.

By dividing the spectrum in to low, mid, mid-high and high frequency (edge rate) zones you can select four capacitors (again, not so much values as much as frequency related characteristics) to cover the range. A typical setup will have electrolytics by the power source (LF), medium-packaged tantalums within 5 to 10 cm of relevant chips (MF to HF) and a couple of small-package chip cap flavors within about 2cm of high-speed chips (HF). The significance of speaking in terms of packages as opposed to values is that the package type becomes the primary factor in such properties as ESL (which is the dominant element as frequencies rise). Small tantalums, for example, like 4.7 to 10uF are absolutely worthless for high-speed decoupling designs. You have to get into the larger packages in order to get decent ESR and ESL characteristics.

What attracted me to #3, aside from the obvious BOM-friendly results, was the fact that you can engineer a much smoother impedance "bucket". Option #2 requires very careful design, modeling and simulation to ensure that you are not creating a real problem or it can produce weird peaky resonant behavior . I wasn't equipped nor inclined to do that and #3 made more sense overall. What's missing in the decoupling cap world are caps with low ESL and not so low ESR (or quantifiable ESR). If you run the curves, you want some ESR to mitigate peaky resonance effects.

Finally, #4, is included in my list because it was something a "professional" PCB designer told me when I was considering using his company's services. The way this person did high-speed layouts was to "make it look good and it will work fine". I would imagine there's a lot of that going on out there. I can only wonder and cringe.

To address the OP's questin directly. There are good guidelines out there on what is required and many options on how to do it. Every layout will be different due to things like the which and how many pins you use. You need to get a set of high-speed decouplers very close to the FPGA, within a 2cm circle, I'd say. Modern 0402 components allow you to place a good number of these within the device's footprint. Fan out from there with mid to low frequency caps to support charge transfer and avoid starving he HF caps. Again, quantity and type depend on your design and edge rates. There are good books out there that cover the basics. One such books is "High Speed Digital Design, a Handbook of Black Magic" by Howard Johnson.

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Fair enough :-)

180ps/in makes out to be 180/25.4 ps/mm ~ 7ps/mm (1.4e8 m/s)

Indeed it would, I think I must have dropped a factor of 10 somewhere, sorry about that! I did the sums properly when I designed the board, honest :-)

Indeed - that's where I learned a lot of this information from...

How about we say that 1-2cm is close enough (for the HF decouplers?)

Agreed - I did much the same thing here.

It's getting better, but there wasn't much useful data when I did this either. I ended up distributing lots of different values of capacitor to get a flat impedance profile - which doesn;t half make your BOM long. And makes population a trial. I'm not sure if I'd do this again unless absolutely necessary!

Agreed - the words "conservative rules" are appropriate... even for low-speed designs (are there any of those any more?) you may be spending too much on your caps.

Right, should have read on before scribbling my earlier paragraph :-)

I would add that the inductance is affected quite strongly by mounting method (number of vias and the inductance of the copper connecting them to the pads) and by the spreading inductance of the planes. Did you take advantage of thin dielectrics for extra high-quality capacitance? We put two 3.3V/GND 4thou separation pairs in the board, which got us a few nF of very low inductance capacitance, which comes in handy at the top end.

I came to the conclusion that above 100-150MHz you couldn't do a lot with capacitors anyway.

You could always fit some small resistors in series :-)

Looks like we came to the same conclusions in the end then!

Frightening. Unless their idea of aesthetically pleasing happens to be trained by what will work ....

And I'd agree now my 10s are in the right place :-)

I can recommend that book also, along with subsribing to the si-list

Apologies again for my arithmetic!

Cheers, Martin

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'been there, done that, paid for it dearly... :-(

That would seem to be the case.

...

What's scary is that no matter how much you research the subject it's hard to achieve convergence. It seems that everyone has a different --and perfectly valid-- reason why it should be done differently. As is the case with many things in engineering you have no choice but to abandon the search for the truth, pick an approach you're comfortable with, and move on.

Did that, exactly.

Probably true for discrete capacitors. I remember looking into these BGA packaged cap arrays that seemed to do quite well at high frequencies.

Funny enough, I did think about this. The more I looked at the calculations and the curves the more I realized that you do want more series resistance with your decouplers. Sort of counter-intuitive in looking at the problem superficially, but makes perfect sense in the context of a power distribution system. Well, I didn't want to be the first fool to try to double-stack 0402 chip caps with 0402 chip resistors. I'll leave that excercise for those who might be substantially better funded than I am (enough to redo a board)! :-)

See what happens when you don't use an RPN calculator!

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Xilinx have a reasonably good app note on this very cap / FPGA / clock thing. search their web site.

Simon

P.S. As a PCB designer of 10 years or more.. I still don't put vias inside pads.. neither do our RF guys working at 1.5 GHz! You are asking for thermal problems doing that. now if you use laser vias or other micro vias or welded joints ... you don't have to worry ... but a standard FR4 PCB with

0.5mm or 0.8mm vias you have to worry. At 1.5 GHz all their designs use 3 0.8mm vias just touching the pad. never misses :-).. just requires a program called ADS from HP.

case

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calculations

XAPP158. Yup. One of the first references I looked at back two years ago. Pretty much spot on. If you want to have a better understanding you have to dive deeper into the subject, of course. For example, XAPP158 does not deal with PDS (power distribution system) design issues that affect signals going from chip to chip in a high-speed design. Noise in mixed-signal designs, etc., etc. Of course, that's not what the app note is about.

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[context is bypass caps]

So what do you do then? 1 ns edge rates are reasonably common now. That's well above 150 MHz.

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Once you get above the package resonance frequency, you have to rely on the chip vendor doing the right thing (witness the caps placed on the package of P4 and Athlon devices for example). I don't know what X and A are doing about this, given the wildly varying things people want to do with their devices at "silly" clock rates...

Cheers, Martin

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