pours under BGAs

Yes, there was a discussion in the German newsgroup de.sci.electronics some time ago about this topic:

I think Google can translate it, but following the web links might be already interesting.

--
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

John Larkin a écrit :

Via in pad seems to be the hot thing of the moment. Different technos are offered. Google for 'via in pad' 'plugged via' 'filled via' 'microvia'

I've a small overcrowded 7mm dia pcb where a 5 balls uBGA opamp, a handfull of 0201s, some huge 0402s and even 2 0603s, not counting the enormous 2 wire soldering pads have to fit. I can only see it fitting with vias in pad.

See:

--
Thanks,
Fred.

snip

snip

yes but it seems like it not so simple, the vias need to be filled or plugged so they don't eat the balls ;)

-Lasse

"John Larkin" wrote in message news: snipped-for-privacy@4ax.com...

A few houses can laser drill, forget the specifics, but I think its

1-2mil. Did a 2812 design many years ago and we used a house in CA for laser drilling.

I see most houses can do 5 mil drills, but I don?t know the cost.

Cheers

[snip]

John, I know a real good layout guy. He's done 18 layer boards for me with multiple FPGA. He is not local to SF, but could probably help out, at least give you some hints. He has worked with multiple board houses. I can put him in touch with you if you want.

--
Joe Chisolm
Marble Falls, Tx.

I put 0402 100nF bypass caps on the opposite side of the board, under the FPGA. The larger caps, >1uF, get mounted on the around the perifery of the FPGA, but I don't worry much about them since they are for the lower freq current components. We use 8mil vias with a 15mil pad and 5 mil rules which the board houses we use have no problem with. $1600 seems pretty reasonable for boards like this.

You can put drill holes in the pads, but this requires filled vias which is an extra step or two to prevent the hole from sucking up solder. I've never had to use filled vias for BGA designs which are about the same complexity as your board.

-- Mark

I prefer to keep them on top, far away enough that we can get our little prism inspection thing in there to scope the balls. Seems to work. I like four 0603, 0.33uF caps per supply. Production hates

0402s.

The larger caps, >1uF, get mounted on the around the

Those rules would sure help. I'll see how our fab houses feel about them. Things change every year or so.

John

The advantage of the 0402's is that you can create a footprint with round pads that 'mirrors' the FPGA pads on the back of the board. This allows you to get a cap directly on most supply/GND pairs.

Is that enough (what sized devices are you using)?

I typically use 3 or 4 caps per bank (on an 8 bank device. ie a reasonably big Cyclone III).

Most assembly houses treat 0402 as run of the mill these days. I don't think this approach has cost me any more in assembly costs although I tend to do a low number of prototypes so am paying a lot for this anyway.

Tell your production to buy some decent assembly machines! :-)

Nial.

I hate backside parts. And if you have decent planes, there's no reason to put the caps very close to the FPGA, much less between the balls on the back side.

Xilinx Spartan6/45, FG484 package. Connected to a PLX PEX8311 PCIe bridge and a DDR dram, both BGA, and a heap of other stuff. We're using pretty much all the i/o's, which makes routing and pouring nasty.

I think that most boards are over-bypassed. I've seen boards with over

1000 bypass caps, which is insane. I know one guy who uses no bypass caps, and his stuff works, too. I have never had a bypassing problem on a multilayer board, and I keep ratcheting down the number of caps.

They are practically little cubes and tend to tombstone. And we like reference designators, which limit the usefulness of small parts like that.

We have two Essemtek (Swiss) semi-auto p+p machines for in-house assembly. I can't see how the assembly machine would make much difference here. We only use 0402's when it makes a difference to signal quality, like for picosecond stuff.

Aeroflex just announced some 0402 schottky diodes, 0.1 and 0.08 pF. Those are worth the hassle.

John

on something like an fg456 spartan2e theres this nice tempting square with no balls, 402s fits between the vias on the back side in the suggested layout,

603 is too big.

but agreed if it is the only thing on the back of the pcb its a big extra step in production to place those part on the back side

seen this?:

suggest that a FG(G)484 LX45 needs 70 bypass caps, though about 50 are for those for the Vccos

or this:

it is for spartan3 don't know if they have a similar for spartan6

snip

-Lasse

Why? We have as many on the back as the front. It saves a lot of money.

That's your theory and in most cases works. You'll get to a point where it won't. I usually have the pads just in case and then no-pop.

I'e seen the same and have done things almost that bad. I only needed ten boards and they *had* to work first time. In that one I used Xilinx' recommendations. It looked like it had 1000 caps. ;-)

pads

Ths S6 chip is solid balls, 22x22, no place for caps. Personally, I don't see any need to put the caps under the FPGA anyhow.

I do plan to solder a micro-coax to supply:ground vias under the FPGA and run to a scope to see the actual supply noise in operation. And we put SMB connector footprints on the major pour pours, so we can scope them, too.

That reminds me of Howard Johnson's book: half good stuff, half nonsense. If you can tell which is which, you don't need the book.

John

I have been doing it for almost a decade now - although on a 1.27mm BGA. But there should be no difference in that respect, I go as low as 4 mil (thus I manage to have 3 traces between two pads, plus a hole in every BGA pad so I can access all signals). I also do put some decoupling 0603 caps underneath the BGA, without overdoing it. I have the holes drilled 0.3 or 0.2mm (I leave the choice to the PCB house, I think they go for 0.2 lately). The only price you pay for being able to do that is that you have to bake all BGA parts with some flux once balls up to make sure all balls are "hot" soldered to the BGA itself, otherwise the "cold" ones flow down the hole... (had this on my first attempt... :-) ).

Here are some photos of such a board:

(top view), (bottom view). This is the prototype, one can see the advantage to have all the signals accessible from beneath :-) .

Dimiter

------------------------------------------------------ Dimiter Popoff Transgalactic Instruments

------------------------------------------------------

Two p+p operations, two passes through the oven, probing nightmare.

It's worked so far. I've got products with eclips-plus logic running at 1 ps RMS jitter, and one product with a signal running in and out of one fpga five times, each pass accumulating jitter, and getting under 30 ps RMS. I routinely TDR bare boards and measure noise on the planes of live boards. I don't think we're pushing the edge of reliability.

Spartan 3's up through the -1500 version, and now a Spartan6/45 on the board we're about to gerber.

The real low impedance structure isn't the caps, it's the power and ground planes. My TDR experiments suggest that it doesn't much matter where you put the bypass caps... within an inch of the FPGA is fine. If I mess up, I'll let everybody know.

Every part vendor thinks his part is the center of the universe.

Have you ever done a multilayer board that had problems because of too few bypasses?

I did have an LDO sawtooth oscillate because of too much ceramic bypassing. That modulated the FPGA core voltage, modulated the prop delays, and caused tons of jitter. A parallel tantalum damped it down.

John

pads

...half the number of boards. Fewer connectors.

You might know when you've crossed it.

That's obvious. Can't have a single point ground under the other guy's part.

Have I? Yes and no. I use decoupling capacitors, though when the stupid tech got the brilliant idea to disregard instructions and daisy chain all power and ground on #30 wires ("See they're all wired to the right voltage" - continuity checker in hand) things got ugly in the boss' office. Do I know of designs that haven't worked because of too few decoupling caps? Youbetcha. Several didn't work at all, some rather more flaky. 74AS shoot-through is a bitch. Lotsa problems with the TTL mainframes (3081 family), too.

We just had to replace some tantalums with ceramics to get by EMC. Legacy stuff is a PITA. Can't get it to work right and can't change it. :-(

...

...

I'd exect the chip vendor to have an app-note discussing this mess with at least one well worked out example of how they did it, probably with minimal layer count.

I think there are 3 issues here.

The first is to get the dog-bone stuff to fit. That's simple arithmetic.

The second is how to get the via grid to fit. Again, that's simple arithmetic. You said "18 od". What's the clearance hole through a plane? A 1 mm grid is 39 mils. 6 mil lines leave 33 mils for the hole. That's huge. (But maybe I'm forgetting something. There are lots of roundups in this area.)

The third issue is getting the tools to do something sensible. You said "pour".

There are two ways to make a plane. The traditional way is to start with all copper and draw/flash the places you don't want copper. That's usually the clearance holes and thermal relief patterns.

The other way is to "pour" the copper on a signal layer by drawing a raster of lines. The catch here is that those lines are on a grid.

Suppose your line width (raster grid spacing) matches the space where you expect copper between two vias. That line also has to match the grid alignment. Say you have a 0.2 mm slot between vias on a 1 mm grid. If the vias are offset by 0.1, that 0.2 m line won't fit. (If that isnt' clear, I'll try again.)

So the first thing to try is setting the drawing grid smaller. That may take a long time to draw all the tiny lines, but it is a good sanity check. If that works, you might "fix" things by moving the BGA to a good alignment.

Also theck the units on the drawing grid. Drawing in real metric vs english converted to metric sometimes makes a big difference.

I've probably overlooked something interesting (and simple)...

--
These are my opinions, not necessarily my employer\'s.  I hate spam.

The problem with recent devices is getting a decent power supply routed in, I use a solid ground so am not worried about that.

On one design I've got 3 different bank voltages, 3.3V, 3.0V, 2.5V and VCC Int, 1.2V. You then also have to get the 4 * PLL suplies isolated/decoupled and routed in (how do you do this cleanly without devices on the back of the board?). This was on a 6 layer board, with most of the user IO routed out (484 pin device so quite a few user IO) so I'm relying on the caps to 'bolster' my supplies.

This very thread was triggered by your concern of the quality of routing of one of your supplies, can you _always_ rely on it being low inductance?

Have you looked at a non ideally routed supply to see what it's like?

...and in the case of Altera and Xilinx reccomend a decoupling strategy that is impossible to comply with _and_ get at all the user IO.

I haven't because I err on the side of caution, but I'd like to know by how much this is. Getting all those decouplers on the back of a device is a pain in the a*se.

Altera have a tool which is supposed to allow you to analyse the impedance of your power distribution networks and thence optimise your decoupling cap selection...

I've only played with this briefly but if it's accurate it's a step in the right direction.

Nial.

and

I was able to push things around, notably to alternate rows of longer and shorter dogbones, to open up some big channels in all the pours. Smaller vias, or vias-in-pads, would be even better. It's just tedious.

And we had a mighty battle with PADS to make it stop using thermals on our ground vias. We wound up NOT declaring the ground plane to be a plane, and pouring our own ground on a routing layer. Grrrrrr.

I commonly TDR and noise test real boards. The results don't align much with "theory."

Yes.

That agrees with my observation that most boards are over-bypassed and most multilayer bypass religions are as good as any other.

It does the common trick of superimposing the RLC models of all the bypass caps, Spice-mode. My TDR measurements suggest this isn't realistic. Close planes make an impressive bypass structure.

Again, has anyone done a multilayer board that failed from too few bypass caps?

John

It's not just as basic as looking at the decoupling caps, it also takes into account, and you can specify, plane dimensions, BGA break out via dimensions and seperation, capacitor mounting style and dimensions (and X2Y cap mounting and dimensions).

The plane and device internal capacitance are used to define a target impedance and frequency below which the supply impedance is defined with caps. The goal is then to hit the target impedance, or lower, with a selection of pre-defined (or user defined) caps.

I was introduced to this in an Altera seminar about designing in their high speed interfaces. One of the things that emerged from playing with the tool was the benefit of using X2Y caps.

Nial