A quick question, based on one of yesterday's threads on DCM jitter -
Does static timing analysis (timingan) factor in DCM jitter?
The Xilinx timing analyser help states under 'Guaranteed Setup and hold requirements' that 'Timing will not include ....., and jitter into guaranteed setup and hold requirements', but it also states elsewhere that clock uncertainty is calculated from INPUT_JITTER and SYSTEM_JITTER
- I couldn't seem to find the clock uncertainty figure in my timing report.
So far, I've treated the timing analyser as a 'golden checker' for my timing requirements - should I then be factoring in, say 200ps of jitter in synth, p&r and timing analysis? I'm running at 100MHz in a Spartan-3.
I'd also be interested in any other fine details of doing these analyses that you folks have to offer - in some of these cases, the devil seems to be in the details :) I'm semi-sure that I've read something somewhere (I couldn't relocate it) about leaving a certain amount of the timing budget left over - ie if you are 1 ps within budget, then you cannot strictly guarantee that the device will work as expected, but I couldn't find any recommendation of this sort in the Timing Closure TechXclusive.