Just feed it a clock and have it generate random bits.
74HC... components preferred... I have most everything in that family in my parts bin ;-)
Thanks! ...Jim Thompson
-- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at
formatting link
| 1962 | I love to cook with wine. Sometimes I even put it in the food.
If pseudo random is good enough, google for LFSR. With the right polynomial, you get a random sequence of (2^N)-1 bits. There are tables of polynomials that do that. Some of them need only 1 XOR gate.
--
These are my opinions, not necessarily my employer's. I hate spam.
--
Whoopeee!!!
Right up my alley!
Do you want truly random or pseudorandom, and if pseudorandom how long
do you want the output to be before it repeats?
Pseudo-random is just fine. I just need it to test an encoding/decoding chip design. A hundred bits or so before repeat would be quite adequate. No security involved... just testing to be sure of no decoding hiccups.
Thanks! ...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I can see November from my house :-)
If you want truly or statistically-close-to-really random, it's a Hard Problem. You'd probably want something like an avalanche or other noise diode, amplified, and then fed into a comparator... shield and filter the >bleep< out of it to keep it from being pulled around by external noise. Latch the output of the comparator on each clock pulse and you've got reasonably random bits.
If you're willing to accept pseudo-random bits (chaotic-looking, but actually predictable), a cheap and easy solution is a maximal-length linear feedback shift register. These require a shift register of suitable width (feel free to daisy-chain several 74HC595 or similar) and an N-input XOR. You simply XOR several of the parallel outputs of the shift register together and feed this back into the shift-register inputs. If you pick these tapped outputs correctly (creating a primitive polynomial mod 2), the output bitstream will have a period of 2^N-1 before it repeats (where N is the width of the shift register).
You have to be careful to pre-load the register with at least one "1" bit at reset time... it'll stick at zero, otherwise.
Schneier's "Applied Cryptography" has a table of suitable primitive polynomials on pages 376-377. Some of them are rather huge... if you want a 3217-bit shift register version, he's got two of them!
There are several which would be pretty easy to implement, and have a good long repeat period... 60 to 64 bits, with at most 5 inputs to the XOR.
For more sophisticated LFSRs, you can:
- Run several of them of different lengths (each with its own feedback chain), and XOR the results.
- Use an "alternating stop and go" generator, which uses three LFSRs of different lengths and feedback taps. One generator "A" is shifted on every clock; its output controls which of the other two "B" and "C" is shifted during that clock; the final output is taken by XORing the output bits of "B" and "C". This architecture has the effect of "hiding" the raw outputs of the LFSRs from visibility, and makes determining the LFSR feedback coefficients quite a bit harder.
--
Dave Platt AE6EO
Friends of Jade Warrior home page: http://www.radagast.org/jade-warrior
I do _not_ wish to receive unsolicited commercial email, and I will
boycott any company which has the gall to send me such ads!
Vladimir, What's your definition of "ugly" ?:-) ...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I can see November from my house :-)
Xilinx XAPP052 - Efficient Shift Registers, LFSR Counters, and Long Pseudo-Random Sequence Generators. Gives tables for LFSR generators from 3 to 168 bits in length.
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I can see November from my house :-)
Try a 74hc164 and a 74hc7266. Connect QF and QG to A input through one of the gates in the 7266. Apply clear and clock to 164. You should get a 127 bit PRBS.
--
Muzaffer Kal
DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com
Horowitz and Hill's "the Art of Electronics" only gives the data for minimal PRBS implementaions from 3 to 40 bit lengths, but does also list the taps required to get a PRBS from 8-, 16-, and 24-bit shift registers (which are easy to realise in 74 series logic).
Thanks! That's pretty much what I had decided... except all the LFSR/PRBS pages are all confusing as hell to an Analog guy :-) ...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I can see November from my house :-)
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here.
All logos and trade names are the property of their respective owners.