Stable Design: The design is translated from a VHDL dalton project
Small Design: Consumes only 324 Flip-Flops: map report #
Fast Design: 50MHz for a xc4vlx25-10 XILINX device: timing report
Stable Design: The design is translated from a VHDL dalton project
Small Design: Consumes only 324 Flip-Flops: map report #
Fast Design: 50MHz for a xc4vlx25-10 XILINX device: timing report
More map report details, from the link : Target Device : xc4vlx25 Number of Slice Flip Flops: 324 out of 21,504 1% Total Number 4 input LUTs: 2,423 out of 21,504 11%
-jg
I don't want to nitpick. It looks like a nice and (maybe more important) little project.
But on the web site I see the following performance figures:
I8051_ALU:
Critical Path Length (ns): 178 Maximum Clock Speed (MHz): 5.63 I have to admit that I'm a FPGA noob, but I think that part deserves some optimization.
Nils
Without reading TFA, I agree, I laughed where it says it's a small design because it only uses 324 FFs, and yet it uses 10 times as many LUTs!
Cheers, Syms.
And some work too....
Quote: Limitations: This implementation is not cycle/timing compatible. Interrupt handling is not currently implemented. Peripheral devices are not currently implemented.
Meindert
)
As far as I remeber this is a multicycle path. But I'll double check.
But I wonder why anyone would want to put such an archaic computing machine in an FPGA (except for academic purposes). There are much better cores available.
JJS
Hans
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