Active Rece\onfiguration of Xilinx FPGAs

Hello

I need some practical info on has any body used Xilinx Vertex series of FPGAs for any project involving active partial reconfiguration

I mean to say that if a part of FPGA is working then can we reconfigure another part of the FPGA and make it work

Rgds Kedar

Reply to
Kedar P. Apte
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Hi Kedar, Partial Reconfiguration can definitely be used on most Xilinx Virtex Series FPGA's - especially in the latter ones. This should be documented under "ICAP Port" in the user guide or the chip documentation available at

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We designed the chips such that sections of your chip can remain active as normal while other sections are being reconfigured. For more practical experience with actually using it - perhaps other members of comp.arch.fpga can share their experiences.

- Vic

"Kedar P. Apte" wrote:

Reply to
Vic Vadi

There's a Xilinx app note with example design files that walks you through the most basic possible use of partial reconfiguration (xapp 260 or 269, something like that).

A while ago I setup the partial-reconfig mailing list dedicated to this topic. It's pretty quiet but feel free to join and start asking questions:

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Regards,

John

Reply to
John Williams

The chips have been designed for partial reconfiguration for a very long time, but the software has not. My understanding is that both the Spartan 3 and the Virtex 4 devices are not supported by modular configuration which is the only practical use of partial configuration unless you are just trying to compress your bit streams.

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Rick "rickman" Collins

rick.collins@XYarius.com
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Reply to
rickman

thanks John

I have subscribed my email for that list let us see I need more info on if any body had done partial reconfiguration in Xilinx when a part of FPGA is already active

So in that details about tools used configuration modes and a bit of hardware configuration required and finally does it work

Thanks alot for your help I will try and post messeges on that also

Rgds Kedar

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Reply to
Kedar P. Apte

Yes it works, it can be done, I've done it, so have many other people. But, it's not easy, in fact it's downright difficult and painful. If you are going to spend effort working on this, you must have a very good reason - only you can be certain of that.

Start by reading this document:

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Once you've read it, then read it again. Probably read it a 3rd time. Then, step through the various steps described, using the simple design files that Xilinx provides.

Until you truly understand every step of the process described in XAPP290, there is simply no point trying to do it yourself, on your own designs etc. I say this from painful experience!

You should also have available the manual for the XST tools - they are distributed in PDF form with ISE. In particular, the options to NGDBUILD, MAP, and PAR, relating to partial reconfiguration are documented. You must read these very carefully - when I first started I looked at them, thought "yes, that's easy", but then couldn't get it to work. The problem was always that I had missed some tiny detail.

Good luck!

John

Reply to
John Williams

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