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How to program and initialize Lattice XP devices

I am planning to use the Lattice XP flash based FPGA in a new design and I have not worked with it before. It seems to be a RAM based FPGA which contains an internal flash for self booting. I need to provide an external JTAG port for factory programming, a system JTAG port for in system programming by an embedded CPU and also allow the XP device to boot itself in normal operation.

I understand how to use the JTAG port and I have set up controls to allow it to be programmed from one of two sources on the JTAG port. But I have not been able to find sufficient info to tell me what to do after the device has been JTAG programmed in system. Once the JTAG port takes over control of the device, how do I exit that mode? The flash will contain the new configuration information, but how do I get the XP device to load the RAM from the flash without cycling power? Is cycling the PROGRAM_N pin sufficient? I am planning to set the CFG pins to 1, 1 for self program mode.

I may have a bit of trouble with this since I am designing a new board to take the place of an older design using a simpler flash based CPLD. In that design the system could drive the JTAG port to reprogram the CPLD. That device would be immediately available with the new load once programming was complete. With the XP device, once the flash is reprogrammed by the system via JTAG, I believe it has to be told to reboot the SRAM from the flash which I don't have a simple way of doing. I may have to share a incoming board pin between a board disable control and the PROGRAM_N control.. if this is what is required to reboot the device.

Anyone here know for sure that toggling the PROGRAM_N pin is needed and sufficient to reload the SRAM from the Flash?

Reply to
rickman
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Yes, it is neded and sufficient. I'm working with an XP device based board as we speak.

Best regards, Maki

Reply to
Maki

Thanks. I guess I am just a bit unsure, not having worked with these parts before. The board disable signal is high for disable. In that state my board should be non-functional in all ways. When the board is to be used or programmed, that line will be low. If I invert the disable signal and use it to drive PROGRAM_N, it will hold the XP in program mode when the board is disabled. Will this cause any problems? I know these parts are similar to the Xilinx parts and they would sit in the initialize state clearing memory continuously until PROGRAM_N is released. I can't find any info on what happens with the Lattice parts. They do list the power consumption in initialization which is around 100 mA combined and over twice as high as in "Standby". But they don't define exactly either of these measurements. I assume the initialization current is about the same while holding the PROGRAM_N pin low as it is after you release it until the DONE pin goes high. I also assume the Standby power is a configured part with no activity.

I'll see what their support says. They seem to be pretty good at getting back in a day or so.

Reply to
rickman

I'd be very surprised if the parts drew as much power while PROGRAM_N is held low as they do while initializing until DONE goes high. The main reason for the extra current is the internal flash memory reading.

Also be aware that the pullups may be active on some pins until the part is programmed. I know this is the case for ECP parts, and that the "weak" pullup current is higher in these parts than in the Xilinx parts I've used in the past.

Reply to
Gabor

That may well be true. But I am pretty sure the chip is very active while PROGRAM_N is low. I will see what support says, if they have any additional info at all.

Then you haven't used the Spartan parts. They have a bug in the pullup resistor values that let them be as low as 1.15 Kohms. Instead of fixing this they decided that users could live with it and documented it as a feature. The newer versions of the Spartan 3 chips have fixed it.

The Lattice XP parts are spec'd at 22 kohms min. This should not be a real problem.

My concern is floating I/Os. It is always hard to find documentation on all the combinations of modes that an FPGA may be in to see how all the various pins are defined. I can't be sure there aren't modes where an I/O is floating. I currently have about 40 pullups and I am looking to get rid of them. So I will be reading every detail of the data sheet that I can find.

Reply to
rickman

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