How to use EAB in Altera FPGA?

Hi all:
I have the following verilog codes which shift the serial data to parallel
data.But it cost
too much LEs in Altera FPGA.Then I want to make it wokes in EAB.I do not
what to do.Anybody would help me?

reg[31:0] reg_in[7:0],reg_out[7:0];

always @(posedge clk)
 begin
  if(reset)
       cnt8<=0;
  else
   if(cnt8==7)
    begin
     cnt8<=0;
     reg_out[0]<=reg_in[0];
     reg_out[1]<=reg_in[1];
     reg_out[2]<=reg_in[2];
     reg_out[3]<=reg_in[3];
     reg_out[4]<=reg_in[4];
     reg_out[5]<=reg_in[5];
     reg_out[6]<=reg_in[6];
     reg_out[7]<=reg_in[7];
    end
   else
    begin
     cnt8<=cnt8+1;
     reg_in[0]<=reg_in[1];
     reg_in[1]<=reg_in[2];
     reg_in[2]<=reg_in[3];
     reg_in[3]<=reg_in[4];
     reg_in[4]<=reg_in[5];
     reg_in[5]<=reg_in[6];
     reg_in[6]<=reg_in[7];
     reg_in[7]<=data_receive;

     end
 end