Hi to all
i am implementing my own DDR 2 @400 controller
my code for BANK AND ADREES lines is while initializing
s_ddram_ba
HI EVERYBODY PLEASE.... HELP REGARDING DDR 2 CONTROLLER
May 25, 2007
1 Replies
snipped-for-privacy@gmail.com schrieb:
Dear sudhakar
a succesful implementation of highperformance DDR2 400 Memory IP in any FPGA is a task that takes at least 6 man-months. How many of those have you already spent?
Do you think somebody can give you "little advice" and you get it working just like that?
When you are SHOUTING to the group, you hardly ever get response.
Antti
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