Hello All! We are newbies to FPGAs and VHDL. We're doing a project on it and we need to have custom hardware for it. We then settled for the FSL solution. We are just starting to work on it.. We wanted to have a very primitive ALU kind of a thing. We set out editing the a template file generated when we create a new peripheral on XPS (We use EDK7.1), which gets 8 input words and returns their sum. We modified the VHDL code to want to it to work this way: get an opcode, get two operands and return the sum or difference based on the opcode. Something kind of this: if(opcode == ) return a+b; else return a * b; But its not working. We tried out many things, but in vain. I'm copy-n-paste-ing the VHDL code here and also the C file. Please help us figure out the problem:
------------------------------------------------------------------------------
-- MyIP - entity/architecture pair
------------------------------------------------------------------------------
--
--
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------------------------------------------------------------------------------
-- Filename: MyIP
-- Version: 1.00.a
-- Description: Example FSL core (VHDL).
-- Date: Mon Mar 13 20:23:40 2006 (by Create and Import Peripheral Wizard Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "I_"
------------------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- FSL_Clk : Synchronous clock
-- FSL_Rst : System reset, should always come from FSL bus
-- FSL_S_Clk : Slave asynchronous clock
-- FSL_S_Read : Read signal, requiring next available input to be read
-- FSL_S_Data : Input data
-- FSL_S_CONTROL : Control Bit, indicating the input data are control word
-- FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL bus
-- FSL_M_Clk : Master asynchronous clock
-- FSL_M_Write : Write signal, enabling writing to output FSL bus
-- FSL_M_Data : Output data
-- FSL_M_Control : Control Bit, indicating the output data are contol word
-- FSL_M_Full : Full Bit, indicating output FSL bus is full
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity MyIP is port ( -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add or delete. FSL_Clk : in std_logic; FSL_Rst : in std_logic; FSL_S_Clk : out std_logic; FSL_S_Read : out std_logic; FSL_S_Data : in std_logic_vector(0 to 31); FSL_S_Control : in std_logic; FSL_S_Exists : in std_logic; FSL_M_Clk : out std_logic; FSL_M_Write : out std_logic; FSL_M_Data : out std_logic_vector(0 to 31); FSL_M_Control : out std_logic; FSL_M_Full : in std_logic -- DO NOT EDIT ABOVE THIS LINE --------------------- );
attribute SIGIS : string; attribute SIGIS of FSL_Clk : signal is "Clk"; attribute SIGIS of FSL_S_Clk : signal is "Clk"; attribute SIGIS of FSL_M_Clk : signal is "Clk";
end MyIP;
------------------------------------------------------------------------------
-- Architecture Section
------------------------------------------------------------------------------
-- In this section, we povide an example implementation of ENITY MyIP
-- that does the following:
--
-- 1. Read all inputs
-- 2. Add each input to the contents of register 'sum' which
-- acts as an accumulator
-- 3. After all the inputs have been read, write out the
-- content of 'sum' into the output FSL bus NUMBER_OF_OUTPUT_WORDS times
--
-- You will need to modify this example or implement a new architecture for
-- ENTITY MyIP to implement your coprocessor
architecture EXAMPLE of MyIP is
-- Total number of input data. constant NUMBER_OF_INPUT_WORDS : natural := 3;
-- Total number of output data constant NUMBER_OF_OUTPUT_WORDS : natural := 1;
type STATE_TYPE is (Idle, Read_Operands, Write_Outputs);
signal state : STATE_TYPE;
-- Accumulator to hold sum of inputs read at any point in time signal sum : std_logic_vector(0 to 31); signal op : std_logic_vector(0 to 31);
-- Counters to store the number inputs read & outputs written signal nr_of_reads : natural range 0 to NUMBER_OF_INPUT_WORDS - 1; signal nr_of_writes : natural range 0 to NUMBER_OF_OUTPUT_WORDS - 1;
-- Stack definition starts ======================= -- The Stack constant MAXSTACK:INTEGER := 256; -- the max stack file length type stack_file is array (MAXSTACK-1 downto 0) of std_logic_vector(0 to 31); -- 256 entry stack. signal TheStack : stack_file;
-- Stack variables and pointers signal sp : std_logic_vector ( 0 to 8-1 ) := (others=>'0') ; -- the stack pointer signal localStart : std_logic_vector ( 0 to 8-1 ) := (others=>'0') ; signal argsStart : std_logic_vector ( 0 to 8-1 ) := (others=>'0') ;
type StackState is (CTRL, DATA, ARGSDATA, LDLOCS); signal nextState : StackState := CTRL; -- first to start with: Ctrl signal.
-- Stack definition ends =========================
begin -- CAUTION: -- The sequence in which data are read in and written out should be -- consistant with the sequence they are written and read in the -- driver's MyIP.c file
FSL_S_Read