FPGA wanted

hi all,

I m looking for a FPGA with a SPI interface. The SPI interface needs to be able to send data at a high rate (10 Mbit/s).

regards Stijn

Reply to
Stijn Goris
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--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com
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"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

Reply to
Ray Andraka

I want to use a RTL8019 chip and want to interface it with a SPI bus (datasheet: ftp://210.51.181.211/cn/nic/rtl8019as/spec-8019as.zip). I 'm having trouble finding a good way to make the SPI communication. Someone stated that an FPGA could do the conversion. Maybee you have a better idea?

kind regards Stijn

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Reply to
Stijn Goris

Hello Ray,

Can you advice a FPGA that can deliver me the 10 Mbit/s?

thanks Stijn

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Reply to
Stijn Goris

Almost any modern FPGA should!

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Reply to
valentin tihomirov

An FPGA certainly can do the conversion, but you'll have to design the circuit to go in the FPGA to do that conversion. The FPGA can be viewed as a big box of uncommitted logic gates. What you hook them up to do is up to the FPGA designer. 10MBits/sec is achievable with any modern FPGA. Pick one based on your costs and comfort with that FPGA's tools.

Stijn Goris wrote:

--

--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com
formatting link

"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

Reply to
Ray Andraka

If this is the only task, a CPLD would be a better fit. IIRC a 8019 is an Ethernet (parallel memory mapped) controller, so you need SPI Adr.Data.RD_WR_Strobes. First steps are to do a pin budget, then define transaction size ( 8/16/24 bits etc ), then how you will map the bus action/direction onto bits inside that frame. Smarter designs can include what amounts to SPI_DMA, where the CPLD can stream data at close to full SPI bandwidth, after being carefully initialised. If it's a 3V system, Xilinx Coolrunner2 devices will draw

Reply to
Jim Granville
10Mb/s is a small cup of tea...

Kelvin

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Reply to
kelvin_xq

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